Patents by Inventor Sola Woo

Sola Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230194594
    Abstract: Measurement data are produced by measuring characteristics of a semiconductor device. Target parameters are selected among a plurality of parameters of a device model where the device model is configured to perform a simulation based on device data and output simulation result data indicating the characteristics of the semiconductor device. Initial value sets corresponding to different combinations of initial values of the target parameters are selected. Local minimum values are determined based on reinforcement learning. Each local minimum value corresponds to a minimum value of a difference between the measurement data and the simulation result data with respect to each initial value set. Optimal values of the target parameters are determined based on the plurality of local minimum values.
    Type: Application
    Filed: August 30, 2022
    Publication date: June 22, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gwangnae GIL, Seyoung PARK, Sola WOO, Jonghyun LEE
  • Publication number: 20230125401
    Abstract: To predict characteristics of a semiconductor device, a simulation current-voltage curve of the semiconductor device is generated using compact models where each compact model generates simulation result data by performing a simulation based on device data. The simulation result data indicate characteristics of semiconductor devices corresponding to the device data. The compact models respectively corresponding to process data and semiconductor products. Simulation reference points on the simulation current-voltage curve are extracted. Basic training data corresponding to a combination of the simulation reference points and the simulation current-voltage curve are generated. A deep learning model is trained based on the basic training data such that the deep learning model outputs a prediction current-voltage curve. A target prediction current-voltage curve is generated based on the deep learning model and target reference points corresponding to the target semiconductor product.
    Type: Application
    Filed: May 11, 2022
    Publication date: April 27, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jonghyun LEE, Gwangnae GIL, Seyoung PARK, Sola WOO
  • Publication number: 20230113207
    Abstract: To predict characteristics of a semiconductor device, basic training data corresponding to a combination of input data and simulation result data are generated using a technology computer aided design (TCAD) simulator. The TCAD simulator generates the simulation result data by performing a simulation based on the input data of the TCAD simulator such that the simulation result data indicates characteristics of semiconductor devices corresponding to the input data of the TCAD simulator. A deep learning model is trained based on the basic training data such that the deep learning model is configured to output prediction data indicating the characteristics of the semiconductor devices. Target prediction data is generated based on the deep learning model and input data corresponding to the target semiconductor product such that the target prediction data indicates the characteristics of the semiconductor device included in the target semiconductor product.
    Type: Application
    Filed: April 19, 2022
    Publication date: April 13, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sola WOO, Gwangnae GIL, Seyoung PARK, Jonghyun LEE
  • Publication number: 20230105438
    Abstract: A method of operating a transistor modeling apparatus includes acquiring sample data corresponding to transistor modeling through a test device; performing machine learning on the sample data and first electrical test (ET) data of a transistor mass production stage; generating second ET data for the transistor modeling as a result of performing the machine learning; and setting a representative value for the transistor modeling among the second ET data.
    Type: Application
    Filed: April 28, 2022
    Publication date: April 6, 2023
    Inventors: Seyoung Park, Gwangnae Gil, Sola Woo, Jonghyun Lee
  • Publication number: 20230108149
    Abstract: A method of operating an electrical test prediction apparatus includes determining a relationship between first electrical test (ET) data, corresponding to at least one shot region comprising a subset of a plurality of semiconductor chips of a wafer, and electrical die sorting (EDS) data, obtained by measuring a state of each chip on the wafer by a testing device, and predicting second ET data, corresponding to an region of the wafer other than the at least one shot region by performing machine learning on the relationship.
    Type: Application
    Filed: May 26, 2022
    Publication date: April 6, 2023
    Inventors: Seyoung Park, Gwangnae Gil, Sola Woo, Jonghyun Lee
  • Publication number: 20230053696
    Abstract: To predict characteristics of a semiconductor device, basic training data corresponding to a combination of process data, device data and simulation result data are generated using a plurality of compact models. Each compact model generates the simulation result data indicating characteristics of a semiconductor device corresponding to the device data by performing simulation based on the device data, the plurality of compact models respectively corresponding to a plurality of process data and a plurality of semiconductor products. A deep learning model is trained based on the basic training data such that the deep learning model outputs prediction data indicating the characteristics of the semiconductor device. Target prediction data indicating characteristics of the semiconductor device included in a target semiconductor product are generated based on the deep learning model, the device data and the process data corresponding to the target semiconductor product.
    Type: Application
    Filed: March 21, 2022
    Publication date: February 23, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jonghyun LEE, Gwangnae GIL, Seyoung PARK, Sola WOO
  • Publication number: 20230056869
    Abstract: To generate a deep learning model, basic training data corresponding to a combination of device data and simulation result data is generated using a compact model that generates the simulation result data indicating characteristics of a semiconductor device corresponding to the device data by performing simulation based on the device data. A deep learning model is trained based on the basic training data such that the deep learning model outputs prediction data indicating the characteristics of the semiconductor device and uncertainty data indicating uncertainty of the prediction data. The deep learning model is retrained based on the uncertainty data. The deep learning model may precisely predict the characteristics of the semiconductor device by training the deep learning model to output the prediction data and the uncertainty data and retraining the deep learning model based on the uncertainty data.
    Type: Application
    Filed: March 8, 2022
    Publication date: February 23, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gwangnae GIL, Seyoung PARK, Sola WOO, Jonghyun LEE
  • Patent number: 10515982
    Abstract: A semiconductor device includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region. The semiconductor device may operate as a switch or a volatile memory according to a gate voltage applied to a gate and a drain voltage applied to a drain.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 24, 2019
    Assignee: Korea University Research and Business Foundation
    Inventors: Sangsig Kim, Kyoungah Cho, Minsuk Kim, Yoonjoong Kim, Sola Woo, Doohyeok Lim
  • Patent number: 10483284
    Abstract: A semiconductor device includes stacked transistors. Each of the transistors includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 19, 2019
    Assignee: Korea University Research and Business Foundation
    Inventors: Sangsig Kim, Kyoungah Cho, Minsuk Kim, Yoonjoong Kim, Sola Woo, Doohyeok Lim
  • Publication number: 20180138200
    Abstract: A semiconductor device includes stacked transistors. Each of the transistors includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Inventors: Sangsig Kim, Kyoungah Cho, Minsuk Kim, Yoonjoong Kim, Sola Woo, Doohyeok Lim
  • Publication number: 20180138199
    Abstract: A semiconductor device includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region. The semiconductor device may operate as a switch or a volatile memory according to a gate voltage applied to a gate and a drain voltage applied to a drain.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Inventors: Sangsig Kim, Kyoungah Cho, Minsuk Kim, Yoonjoong Kim, Sola Woo, Doohyeok Lim