Abstract: A method includes: receiving a simulation vector associated with a circuit design, wherein the simulation vector is associated with a simulation vector type; identifying, by a processor, a plurality of glitch transitions from among one or more transitions associated with a pin of a cell of the circuit design during a clock period of the simulation vector, and determining a glitch power consumption of the cell during the clock period based on the plurality of glitch transitions.

Abstract: A method includes generating a plurality of input vectors based on input signals to an electric circuit, selecting a subset of the plurality of input vectors, and determining a plurality of datapoints based on the selected subset of the plurality of input vectors. Each datapoint of the plurality of datapoints indicates a power consumption of the electric circuit corresponding to an input vector of the selected subset of the input vectors. The method also includes generating, by a processor, a plurality of vector sequences based on the selected subset of the plurality of input vectors. Each vector sequence of the plurality of vector sequences includes a portion of the selected subset of the plurality of input vectors arranged chronologically. The method further includes training a machine learning model based on a first subset of the plurality of vector sequences and a corresponding first subset of the plurality of datapoints.

Abstract: A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles; determining, by a processor, inferred logic vectors including inferred logic values corresponding to signals output by cells of the IC design based on propagating the recorded logic values of the recorded logic vectors through the cells; and computing per-cycle power characteristics of the IC design based on the recorded logic vectors and the inferred logic vectors.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A method includes acquiring timing analysis data associated with a cell and activity data of one or more inputs of the cell, determining a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs of the cell and the timing analysis data, and estimating a glitch power based on at least the glitch toggle rate.

Abstract: A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles; determining, by a processor, inferred logic vectors including inferred logic values corresponding to signals output by cells of the IC design based on propagating the recorded logic values of the recorded logic vectors through the cells; and computing per-cycle power characteristics of the IC design based on the recorded logic vectors and the inferred logic vectors.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A method includes generating a plurality of vector sequences based on input signals of an electric circuit design and encoding the plurality of vector sequences. The method also includes clustering the plurality of encoded vector sequences into a plurality of clusters and selecting a set of encoded vector sequences from the plurality of clusters. The method further includes selecting a first set of vector sequences corresponding to the selected set of encoded vector sequences, selecting a second set of vector sequences from the plurality of vector sequences not in the first set of encoded vector sequences, and training, by a processing device, a machine learning model to predict power consumption using the first and second sets of vector sequences.

Abstract: Glitch source identification and ranking is provided by: identifying a plurality of glitch sources in a circuit layout; back referencing the plurality of glitch sources to corresponding lines in a Resistor Transistor Logic (RTL) file defining the plurality of glitch sources; identifying, in the circuit layout, a plurality of glitch terminuses associated with the plurality of glitch sources; determining a plurality of glitch power consumption values associated with the plurality of glitch sources based on fanouts in the circuit layout extending from the plurality of glitch sources to the plurality of glitch terminuses; ranking, by a processor, the plurality of glitch sources based on corresponding glitch power consumption values of the plurality of glitch power consumption values corresponding to individual glitch sources of the plurality of glitch sources; and reporting the corresponding lines in the RTL file associated with the ranked plurality of glitch sources.

Abstract: A method includes generating a plurality of vector sequences based on input signals of an electric circuit design and encoding the plurality of vector sequences. The method also includes clustering the plurality of encoded vector sequences into a plurality of clusters and selecting a set of encoded vector sequences from the plurality of clusters. The method further includes selecting a first set of vector sequences corresponding to the selected set of encoded vector sequences, selecting a second set of vector sequences from the plurality of vector sequences not in the first set of encoded vector sequences, and training, by a processing device, a machine learning model to predict power consumption using the first and second sets of vector sequences.

Abstract: A method includes generating a plurality of input vectors based on input signals to an electric circuit, selecting a subset of the plurality of input vectors, and determining a plurality of datapoints based on the selected subset of the plurality of input vectors. Each datapoint of the plurality of datapoints indicates a power consumption of the electric circuit corresponding to an input vector of the selected subset of the input vectors. The method also includes generating, by a processor, a plurality of vector sequences based on the selected subset of the plurality of input vectors. Each vector sequence of the plurality of vector sequences includes a portion of the selected subset of the plurality of input vectors arranged chronologically. The method further includes training a machine learning model based on a first subset of the plurality of vector sequences and a corresponding first subset of the plurality of datapoints.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: Glitch source identification and ranking is provided by: identifying a plurality of glitch sources in a circuit layout; back referencing the plurality of glitch sources to corresponding lines in a Resistor Transistor Logic (RTL) file defining the plurality of glitch sources; identifying, in the circuit layout, a plurality of glitch terminuses associated with the plurality of glitch sources; determining a plurality of glitch power consumption values associated with the plurality of glitch sources based on fanouts in the circuit layout extending from the plurality of glitch sources to the plurality of glitch terminuses; ranking, by a processor, the plurality of glitch sources based on corresponding glitch power consumption values of the plurality of glitch power consumption values corresponding to individual glitch sources of the plurality of glitch sources; and reporting the corresponding lines in the RTL file associated with the ranked plurality of glitch sources.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A method for calculating switching interface activity format (SAIF) for a circuit design includes segregating the circuit design into a plurality of hardware look up tables (LUTs), inserting switching interface activity format (SAIF) counter logic, and inserting a multiplexer between the LUTs and the SAIF counter logic. The SAIF counter logic includes shadow logic, at least one counter, and memory. The method further includes (i) selecting a previously-unselected LUT by switching the multiplexer to the selected LUT, (ii) executing a test through the selected LUT and the SAIF counter logic to generate SAIF data for the LUT, (iii) storing the SAIF data for the selected LUT in the memory, and (iv) continuing with (i) through (iii) until each of the plurality of LUTs is selected. The method further involves merging the SAIF data from each selected LUT into a consolidated SAIF file with SAIF data for the circuit design.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A system and methods provide for an analysis of at least a portion of an integrated circuit (IC) that comprises a plurality of modules, for the purpose of identifying signals that can be indicative of the activity of the modules. By analyzing the activity of these signal immediately before and immediately after each module going from non-idle to idle and from idle to non-idle respectively, it is possible to determine which signals provide an indication that the module should be shut down. If the module can be shut down in idle state, then these input signals may be used as control signals for this purpose. By reporting to a designer the role of such signals a simple design change for detecting the activity and controlling the module, can save on power consumption, in ways not previously detected by the designer.

Abstract: A system and methods provide for an analysis of at least a portion of an integrated circuit (IC) that comprises a plurality of modules, for the purpose of identifying signals that can be indicative of the activity of the modules. By analyzing the activity of these signal immediately before and immediately after each module going from non-idle to idle and from idle to non-idle respectively, it is possible to determine which signals provide an indication that the module should be shut down. If the module can be shut down in idle state, then these input signals may be used as control signals for this purpose. By reporting to a designer the role of such signals a simple design change for detecting the activity and controlling the module, can save on power consumption, in ways not previously detected by the designer.

Abstract: The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.