Patents by Inventor Somesh Peri

Somesh Peri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10622368
    Abstract: Azimuthally-split metal-semiconductor alloy floating gate electrodes can be formed by providing an alternating stack of insulating layers and spacer material layers, forming a dielectric separator structure extending through the alternating stack, and forming memory openings that divides the dielectric separator structure into a plurality of dielectric separator structures. The spacer material layers are formed as, or are replaced with, electrically conductive layers, which are laterally recessed selective to the insulating layers and the plurality of dielectric separator structures to form a pair of lateral cavities at each level of the electrically conductive layers in each memory opening. After formation of a blocking dielectric layer, a pair of physically disjoined metal-semiconductor alloy portions are formed in each pair of lateral cavities as floating gate electrodes. A tunneling dielectric layer and a semiconductor channel layer is subsequently formed in each memory opening.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 14, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Kanakamedala, Raghuveer S. Makala, Rahul Sharangpani, Somesh Peri, Yao-Sheng Lee, James Kai
  • Publication number: 20190371803
    Abstract: Azimuthally-split metal-semiconductor alloy floating gate electrodes can be formed by providing an alternating stack of insulating layers and spacer material layers, forming a dielectric separator structure extending through the alternating stack, and forming memory openings that divides the dielectric separator structure into a plurality of dielectric separator structures. The spacer material layers are formed as, or are replaced with, electrically conductive layers, which are laterally recessed selective to the insulating layers and the plurality of dielectric separator structures to form a pair of lateral cavities at each level of the electrically conductive layers in each memory opening. After formation of a blocking dielectric layer, a pair of physically disjoined metal-semiconductor alloy portions are formed in each pair of lateral cavities as floating gate electrodes. A tunneling dielectric layer and a semiconductor channel layer is subsequently formed in each memory opening.
    Type: Application
    Filed: August 3, 2016
    Publication date: December 5, 2019
    Inventors: Senaka Kanakamedala, Raghuveer S. Makala, Rahul Sharangpani, Somesh Peri, Yao-Sheng Lee, James Kai
  • Patent number: 10355139
    Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. An electrically conductive, amorphous barrier layer can be formed prior to formation of a metal fill material layer to provide a diffusion barrier that reduces fluorine diffusion between the metal fill material layer and memory films of memory stack structures. The electrically conductive, amorphous barrier layer can be an oxygen-containing titanium compound or a ternary transition metal nitride.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Keerti Shukla, Fei Zhou, Somesh Peri
  • Patent number: 9984963
    Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a backside blocking dielectric layer is formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A cobalt metal portion can be formed in each backside recess. Each backside recess can be filled with a portion of a backside blocking dielectric layer, a metallic barrier material portion, a cobalt metal portion, and a metallic material portion including a material other than cobalt.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: May 29, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Somesh Peri, Rahul Sharangpani, Raghuveer S. Makala, Senaka Kanakamedala, Keerti Shukla
  • Patent number: 9893081
    Abstract: After formation of a memory opening through an alternating stack of insulating layers and sacrificial material layers, a blocking dielectric having a greater thickness at levels of the insulating layers than at levels of the sacrificial material layers is formed around, or within, the memory opening. A memory stack structure is formed within the memory opening. Backside recesses are formed by removing the sacrificial material layers and surface portions of the blocking dielectric to form backside recesses including vertically expanded end portions. Electrically conductive layers are formed within the backside recesses. Each of the electrically conductive layers is a control gate electrode which includes a uniform thickness portion and a ridged end portion having a greater vertical extent than the uniform thickness region. The ridged end portion laterally surrounds the memory stack structure and provides a longer gate length for the control gate electrodes for the memory stack structure.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 13, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Kanakamedala, Rahul Sharangpani, Raghuveer S. Makala, Somesh Peri, Yao-Sheng Lee
  • Publication number: 20180040623
    Abstract: Azimuthally-split metal-semiconductor alloy floating gate electrodes can be formed by providing an alternating stack of insulating layers and spacer material layers, forming a dielectric separator structure extending through the alternating stack, and forming memory openings that divides the dielectric separator structure into a plurality of dielectric separator structures. The spacer material layers are formed as, or are replaced with, electrically conductive layers, which are laterally recessed selective to the insulating layers and the plurality of dielectric separator structures to form a pair of lateral cavities at each level of the electrically conductive layers in each memory opening. After formation of a blocking dielectric layer, a pair of physically disjoined metal-semiconductor alloy portions are formed in each pair of lateral cavities as floating gate electrodes. A tunneling dielectric layer and a semiconductor channel layer is subsequently formed in each memory opening.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: Senaka Kanakamedala, Raghuveer S. Makala, Rahul Sharangpani, Somesh Peri, Yao-Sheng Lee
  • Publication number: 20180040627
    Abstract: After formation of a memory opening through an alternating stack of insulating layers and sacrificial material layers, a blocking dielectric having a greater thickness at levels of the insulating layers than at levels of the sacrificial material layers is formed around, or within, the memory opening. A memory stack structure is formed within the memory opening. Backside recesses are formed by removing the sacrificial material layers and surface portions of the blocking dielectric to form backside recesses including vertically expanded end portions. Electrically conductive layers are formed within the backside recesses. Each of the electrically conductive layers is a control gate electrode which includes a uniform thickness portion and a ridged end portion having a greater vertical extent than the uniform thickness region. The ridged end portion laterally surrounds the memory stack structure and provides a longer gate length for the control gate electrodes for the memory stack structure.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 8, 2018
    Inventors: Senaka Kanakamedala, Rahul Sharangpani, Raghuveer S. Makala, Somesh Peri, Yao-Sheng Lee
  • Publication number: 20170373197
    Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. An electrically conductive, amorphous barrier layer can be formed prior to formation of a metal fill material layer to provide a diffusion barrier that reduces fluorine diffusion between the metal fill material layer and memory films of memory stack structures. The electrically conductive, amorphous barrier layer can be an oxygen-containing titanium compound or a ternary transition metal nitride.
    Type: Application
    Filed: October 12, 2016
    Publication date: December 28, 2017
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Keerti Shukla, Fei Zhou, Somesh Peri
  • Patent number: 9842907
    Abstract: An alternating stack of insulating layers and sacrificial material layers can be formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers from the backside trench selective to the insulating layers. A cobalt-semiconductor alloy portion is formed in each backside recess by reacting cobalt and a semiconductor material. Conductive material in the backside trench can be removed by an etch to electrically isolate cobalt-containing alloy portions located in different backside recesses. Electrically conductive layers including a respective cobalt-semiconductor alloy portion can be employed as word lines of a three-dimensional memory device.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: December 12, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Sateesh Koka, Zhenyu Lu, Somesh Peri, Rahul Sharangpani
  • Patent number: 9812463
    Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: November 7, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Senaka Kanakamedala, Fei Zhou, Somesh Peri, Masanori Tsutsumi, Keerti Shukla, Yusuke Ikawa, Kiyohiko Sakakibara, Eisuke Takii
  • Patent number: 9806089
    Abstract: Metal floating gate electrodes can be formed for a three-dimensional memory device by forming a memory opening having lateral recesses at levels of spacer material layers between insulating layers, depositing a continuous metal layer, and inducing diffusion and agglomeration of the metal into the lateral recesses to form discrete metal portions employing an anneal process. The metallic material can migrate and form the discrete metal portions due to surface tension, which operates to minimize the surface area of the metallic material. Optionally, two or more continuous metal layers can be employed to form discrete metal portions including at least two metals. Optionally, a selective metal deposition process can be performed to deposit additional metal portions including a different metallic material on the discrete metal portions. The metal floating gate electrodes can be formed without employing an etch process. A tunneling dielectric layer and a semiconductor channel can be subsequently formed.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: October 31, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Somesh Peri, Raghuveer S. Makala, Yanli Zhang
  • Patent number: 9793139
    Abstract: A silicon-containing nucleation layer can be employed to provide a self-aligned template for selective deposition of tungsten within backside recesses during formation of a three-dimensional memory device. The silicon-containing nucleation layer may remain as a silicon layer, converted into a tungsten silicide layer, or replaced with a tungsten nucleation layer. Tungsten deposition can proceed only on the surface of the silicon-containing nucleation layer or a layer derived therefrom in a subsequent tungsten deposition process.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 17, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Keerti Shukla, Raghuveer S. Makala, Somesh Peri, Yao-Sheng Lee
  • Patent number: 9780182
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A molybdenum-containing portion can be formed in each backside recess. Each backside recess can be filled with a molybdenum-containing portion alone, or can be filled with a combination of a molybdenum-containing portion and a metallic material portion including a material other than molybdenum.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 3, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Somesh Peri, Raghuveer S. Makala, Sateesh Koka, Yao-Sheng Lee, Johann Alsmeier, George Matamis
  • Publication number: 20170278859
    Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.
    Type: Application
    Filed: August 29, 2016
    Publication date: September 28, 2017
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Senaka KANAKAMEDALA, Fei ZHOU, Somesh PERI, Masanori TSUTSUMI, Keerti SHUKLA, Yusuke IKAWA, Kiyohiko SAKAKIBARA, Eisuke TAKII
  • Patent number: 9754958
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: September 5, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jayavel Pachamuthu, Sateesh Koka, Raghuveer S. Makala, Somesh Peri
  • Patent number: 9698152
    Abstract: A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region. At least one conductive material portion can be formed in the remaining volume of the contact trench to form a contact via structure. Alternatively or additionally, a contact via structure can include a tensile stress-generating portion and a conductive material portion. In case the contact via structure is formed through an alternating stack of insulating layers and electrically conductive layers that include a compressive stress-generating material, the tensile stress-generating portion can at least partially cancel the compressive stress generated by the electrically conductive layers. The conductive material portion of the contact via structure can include a metallic material or a doped semiconductor material.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 4, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Somesh Peri, Sateesh Koka, Raghuveer S. Makala, Rahul Sharangpani, Matthias Baenninger, Jayavel Pachamuthu, Johann Alsmeier
  • Patent number: 9659955
    Abstract: A method of forming a device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, and forming an aluminum oxide layer on sidewall surfaces of the sacrificial material layers and on sidewall surfaces of the insulating layers around the memory opening. First aluminum oxide portions of the aluminum oxide layer are located on sidewall surfaces of the sacrificial material layers, and second aluminum oxide portions of the aluminum oxide layer are located on sidewalls of the insulating layers. The method also includes removing the second aluminum oxide portions at a greater etch rate than the first aluminum oxide portions employing a selective etch process, such that all or a predominant portion of each first aluminum oxide portion remains after removal of the second aluminum oxide portions.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: May 23, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Sateesh Koka, Raghuveer S. Makala, Somesh Peri, Senaka Kanakamedala
  • Patent number: 9646975
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers through the backside trench selective to the insulating layers. A cobalt portion is formed in each backside recess. A cobalt-semiconductor alloy portion can be formed on each cobalt portion by depositing a semiconductor material layer on the cobalt portions and reacting the semiconductor material with surface regions of the cobalt portions. A residual portion of the cobalt-semiconductor alloy formed above the alternating stack can be removed by an anisotropic etch or by a planarization process. A combination of a cobalt portion and a cobalt-semiconductor alloy portion within each backside recess can be employed as a word line of a three-dimensional memory device.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: May 9, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Somesh Peri, Sateesh Koka, Raghuveer S. Makala
  • Publication number: 20170125538
    Abstract: A silicon-containing nucleation layer can be employed to provide a self-aligned template for selective deposition of tungsten within backside recesses during formation of a three-dimensional memory device. The silicon-containing nucleation layer may remain as a silicon layer, converted into a tungsten silicide layer, or replaced with a tungsten nucleation layer. Tungsten deposition can proceed only on the surface of the silicon-containing nucleation layer or a layer derived therefrom in a subsequent tungsten deposition process.
    Type: Application
    Filed: March 31, 2016
    Publication date: May 4, 2017
    Inventors: Rahul SHARANGPANI, Keerti SHUKLA, Raghuveer S. MAKALA, Somesh PERI, Yao-Sheng LEE
  • Publication number: 20170125437
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Jayavel Pachamuthu, Sateesh Koka, Raghuveer S. Makala, Somesh Peri