Patents by Inventor Someshwar DK

Someshwar DK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Computer-implemented verification system for performing a functional verification of an integrated circuit
    Patent number: 9460261
    Abstract: A computer-implemented verification system for performing a system level or a system on chip level functional verification of integrated circuit is provided. The computer-implemented system includes one or more processors and a memory storing instructions defined by one or more modules of including a scenario compiler, a verification component and a software library component. The scenario compiler receives a set of verification scenario intents including at least one of test-application intents, constraints, device-programming intents and scenario-control intents. The scenario compiler generates one or more open verification methodology (OVM) and/or universal verification methodology (UVM) compliant test bench sequences and one or more scenario software implementations based on the set of verification scenario intents. The verification component interacts with the integrated circuit using the OVM and/or UVM compliant test bench sequences.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 4, 2016
    Inventors: Srivatsan Raghavan, Karthick Gururaj, Sandeep Pendharkar, Someshwar DK, Shrinivas Nagaraddi
  • COMPUTER-IMPLEMENTED VERIFICATION SYSTEM FOR PERFORMING A FUNCTIONAL VERIFICATION OF AN INTEGRATED CIRCUIT
    Publication number: 20150310159
    Abstract: A computer-implemented verification system for performing a system level or a system on chip level functional verification of integrated circuit is provided. The computer-implemented system includes one or more processors and a memory storing instructions defined by one or more modules of including a scenario compiler, a verification component and a software library component. The scenario compiler receives a set of verification scenario intents including at least one of test-application intents, constraints, device-programming intents and scenario-control intents. The scenario compiler generates one or more open verification methodology (OVM) and/or universal verification methodology (UVM) compliant test bench sequences and one or more scenario software implementations based on the set of verification scenario intents. The verification component interacts with the integrated circuit using the OVM and/or UVM compliant test bench sequences.
    Type: Application
    Filed: March 4, 2015
    Publication date: October 29, 2015
    Inventors: Srivatsan Raghavan, Karthick Gururaj, Sandeep Pendharkar, Someshwar DK, Shrinivas Nagaraddi