Abstract: A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Abstract: Simulated objects are generated for display over a video stream by receiving a first user input that identifies one or more user identified regions relative to an image, tagging each of the one or more user identified regions with a corresponding region tag, receiving a second user input that is used to identify one or more simulation parameters, and identifying one or more simulation parameters based at least in part on the second user input. The method includes determining a plurality of characteristics of the simulated objects based on the simulation parameters, user identified regions and region tags. The simulated objects are superimposed on the video stream to create an augmented video stream and the augmented video stream is processed using one or more video analytics algorithms to test the effectiveness of each of the one or more video analytics algorithms.

Abstract: Embodiments of the invention are directed to a computer system having a processor communicatively coupled to a memory. The processor performs processor operations that include accessing an electronic file that includes an electronic integrated circuit (IC) design. The electronic file is operable to control a fabrication system to fabricate an IC according to the electronic IC design. The processor operations further includes applying a bulging predication analysis to the electronic IC design; and making one or more changes to the electronic IC design based at least in part on a result of the bulging prediction analysis.

Abstract: A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

Abstract: A spatial hierarchical model provides spatial context to a plurality of building control assets disposed within a plurality of hierarchical levels of the spatial hierarchical model. A method includes identifying non-compliance events detected by building control assets disposed at and below a particular hierarchical level of the spatial hierarchical model. The non-compliance events detected by building control assets disposed at and below the particular hierarchical level of the spatial hierarchical model over a period of time are aggregated and a healthy building dashboard that includes a representation of the aggregated non-compliance events for each of at least some of the one or more of the healthy building criteria detected by building control assets disposed at and below the particular hierarchical level of the spatial hierarchical model is generated and is displayed on a display.

Abstract: Structures in semiconductor devices, and methods for forming the structures, are described. In one embodiment, a hard mask layer of a deposition stack can be etched to pattern a hard mask. An interconnect layer of the deposition stack can be etched using the hard mask to pattern a plurality of metal lines. The hard mask can be removed. A liner layer of the deposition stack can be etched to remove a portion of the liner layer deposited directly on a dielectric layer of the deposition stack. In response to etching the liner layer, a remaining portion of the liner layer can be deposited between the metal lines and the dielectric layer.

Abstract: A method of making a back-end-of-line (BEOL) component includes filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material. The method further includes forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material. The method further includes removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material. The method further includes recessing the layer of metal material where the top surface of the layer of metal material is exposed. The method further includes removing the scaffolding material.

Abstract: A semiconductor structure includes a handler substrate and a device substrate bonded to the handler substrate. The handler substrate comprises a trench, and at least one alignment mark in a bottom surface of the trench. One or more dielectric layers are disposed in the trench and on the at least one alignment mark.

Abstract: A semiconductor device includes a transistor structure comprising a plurality of source/drain regions. Base portions of the plurality of source/drain regions correspond to a second side of the semiconductor device opposite to a first side of the semiconductor device. A plurality of metal lines are disposed on the second side of the semiconductor device, wherein the plurality of metal lines comprise at least a first metal line and a second metal line. At least one dielectric layer is disposed between the first metal line and the second metal line.

Abstract: Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.

Abstract: A semiconductor structure includes a substrate; a spacer protruding from the substrate and surrounding a cavity; and spin-on glass filling a portion of the cavity.

Abstract: An approach to form a semiconductor structure with a plurality of buried power rails in a semiconductor substrate where at least one buried power rail extends below the backside of the semiconductor substrate. The semiconductor structure provides at least one portion of the first metal layer of the backside power delivery network that surrounds a bottom portion of the buried power rail below the backside of the semiconductor substrate. The bottom portion of the buried power rail is in direct contact with the portion of the first metal layer of the backside power delivery network where the buried power rail and the first metal layer are composed of the same conductive material. The semiconductor structure includes a portion of an interlayer dielectric material isolating the first metal layer of the backside power distribution network from the backside of the semiconductor substrate.

Abstract: A spatial hierarchical model provides spatial context to a plurality of building control assets disposed within a plurality of hierarchical levels of the spatial hierarchical model. A method includes identifying non-compliance events detected by building control assets disposed at and below a particular hierarchical level of the spatial hierarchical model. The non-compliance events detected by building control assets disposed at and below the particular hierarchical level of the spatial hierarchical model over a period of time are aggregated and a healthy building dashboard that includes a representation of the aggregated non-compliance events for each of at least some of the one or more of the healthy building criteria detected by building control assets disposed at and below the particular hierarchical level of the spatial hierarchical model is generated and is displayed on a display.

Abstract: A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

Abstract: A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

Abstract: A first source drain region adjacent to a first transistor, a second source drain region adjacent to a second transistor, an upper source drain contact above the first source drain region, a bottom source drain contact below the second source drain region, the bottom and the upper source drain contacts are on opposite sides, a horizontal surface of the bottom source drain contact is adjacent to a horizontal surface of dielectric side spacers surrounding the second source drain region. An embodiment where a bottom source drain contact surrounds vertical sides of a source drain region. A method including forming a forming a first and a second nanosheet stacks, forming a top source drain contact to a first source drain region adjacent to the first nanosheet stack, forming a bottom source drain contact to a lower horizontal surface of a second source drain region adjacent to the second nanosheet stack.

Abstract: A first and a second source drain region, an upper source drain contact connected to the first source drain region, a bottom source drain contact connected to the second source drain region, a dielectric spacer surrounds opposite vertical side surfaces of the bottom source drain contact and overlaps a vertical side surface and a lower horizontal surface of a bottom isolation region. A width of the bottom source drain contact wider than a width of the second source drain. Forming an undoped silicon buffer epitaxy in an opening between and below a first and a second nanosheet stack, forming a contact to a first source drain adjacent to that, removing the undoped silicon buffer epitaxy below a second source drain between the first and the second nanosheet stack, forming a bottom contact to that, a width of the bottom contact is wider than a width of the second source drain.

Abstract: A semiconductor structure including a middle-of-line contact, a backside power rail, and a contact via extending between the middle-of-line contact and the backside power rail, wherein the contact via comprises a first portion having a negative tapered profile and a second portion having a positive tapered profile.

Abstract: A method can include obtaining characteristic data for a wafer. The characteristic data can correspond to the wafer in a processed state and can include a set of stress values of the wafer. The wafer can include a front side, a back side opposite the front side, and a set of regions. The set of stress values can include a first stress value corresponding to a first region. In the processed state, one or more front-side processes can be completed on the front side of the wafer. The method can include determining that the first stress value exceeds a stress threshold and generating a compensation map. The compensation map can identify one or more regions for forming one or more trenches. The method can include initiating, based on the compensation map, a formation of a first trench on the back side of the wafer in the first region.

Abstract: A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.