Patents by Inventor Somnath Kundu

Somnath Kundu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220393688
    Abstract: An apparatus and method are provided to re-configure an existing low-jitter phase locked loop (PLL) circuit for fast start-up during system wake-up. During system start-up, a feed-back path of the PLL is disconnected to independently control the VCO frequency. This independently controlled VCO then injects energy into a resonator (e.g., a crustal oscillator) for its fast start-up. Once a resonance frequency of the resonator is detected and an oscillation builds up in the resonator, a VCO control voltage is stored. The PLL feedback is then restored and the stored VCO control voltage is applied to perform phase-locking operation. Since the PLL control voltage is already set to the desired operating point, the PLL lock time is very small.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 8, 2022
    Applicant: Intel Corporation
    Inventors: Somnath Kundu, Hao Luo, Brent Carlton
  • Publication number: 20220229495
    Abstract: Techniques for radiofrequency (RF) touch and gesture recognition are disclosed. In the illustrative embodiment, RF transmitters and receivers are connected to data lines and gate lines of a display. RF signals sent on one data or gate line may be scattered to a different data or gate line based on the presence of a nearby object, such as a finger. The amount of scattering on different data or gate lines can be used to determine a location of one or more objects.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 21, 2022
    Applicant: Intel Corporation
    Inventors: Hao Luo, Somnath Kundu, Brent Carlton, Zhen Zhou
  • Publication number: 20220085822
    Abstract: A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 17, 2022
    Applicant: Intel Corporation
    Inventors: Somnath Kundu, Abhishek Agrawal, Brent Carlton
  • Patent number: 11277143
    Abstract: A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Somnath Kundu, Abhishek Agrawal, Brent Carlton
  • Patent number: 11205995
    Abstract: An apparatus injects a start clock to a crystal at the beginning to increase an overall start up speed of the crystal. The apparatus relies on an impedance change inside the crystal itself instead of searching for a synchronization on the yet small crystal oscillation. The apparatus includes an oscillator (separate from the crystal) to search for the crystal's resonance frequency by detecting the crystal's impedance change. Once the frequency of the oscillator matches the crystal's resonance, there is significant change in the crystal's impedance. Using that information, the apparatus can lock the oscillator frequency at the crystal resonance frequency and inject the clock with high efficiency.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Brent Carlton, Hao Luo, Somnath Kundu
  • Publication number: 20210305939
    Abstract: An apparatus injects a start clock to a crystal at the beginning to increase an overall start up speed of the crystal. The apparatus relies on an impedance change inside the crystal itself instead of searching for a synchronization on the yet small crystal oscillation. The apparatus includes an oscillator (separate from the crystal) to search for the crystal's resonance frequency by detecting the crystal's impedance change. Once the frequency of the oscillator matches the crystal's resonance, there is significant change in the crystal's impedance. Using that information, the apparatus can lock the oscillator frequency at the crystal resonance frequency and inject the clock with high efficiency.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Applicant: Intel Corporation
    Inventors: Brent Carlton, Hao Luo, Somnath Kundu
  • Patent number: 10972109
    Abstract: A sub-sampler phase locked loop (SSPLL) system having a frequency locking loop (FLL) and a phase locked loop (PLL) is disclosed. The FLL is configured to detect frequency variations between a phase locked loop (PLL) output signal and a reference frequency and automatically generate a pulsed correction signal upon the detected frequency variations and apply the pulsed correction signal to a voltage controlled oscillator (VCO) control voltage. The PLL is configured to generate the PLL output signal based on the VCO control voltage.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: April 6, 2021
    Assignee: Apple Inc.
    Inventors: Somnath Kundu, Stefano Pellerano, Abhishek Agrawal
  • Patent number: 10938396
    Abstract: A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: March 2, 2021
    Assignee: Apple Inc.
    Inventors: Abhishek Agrawal, Alon Cohen, Gil Horovitz, Somnath Kundu, Run Levinger, Stefano Pellerano, Jahnavi Sharma, Evgeny Shumaker, Izhak Hod
  • Publication number: 20200295765
    Abstract: A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Inventors: Abhishek Agrawal, Alon Cohen, Gil Horovitz, Somnath Kundu, Run Levinger, Stefano Pellerano, Jahnavi Sharma, Evgeny Shumaker, Izhak Hod
  • Publication number: 20200083892
    Abstract: A sub-sampler phase locked loop (SSPLL) system having a frequency locking loop (FLL) and a phase locked loop (PLL) is disclosed. The FLL is configured to detect frequency variations between a phase locked loop (PLL) output signal and a reference frequency and automatically generate a pulsed correction signal upon the detected frequency variations and apply the pulsed correction signal to a voltage controlled oscillator (VCO) control voltage. The PLL is configured to generate the PLL output signal based on the VCO control voltage.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Somnath Kundu, Stefano Pellerano, Abhishek Agrawal
  • Patent number: 10284395
    Abstract: A time-based decision feedback equalizer (TB-DFE) circuit may include a voltage-to-time converter configured to convert a communication signal into a time-based signal. A timing of when an edge of the time-based signal occurs is indicative of a voltage level of the communication signal. The circuit may include a plurality of delay circuits arranged to process the time-based signal in series to generate a delay data signal. The delay circuits may adjust the timing of when the edge of the time-based signal occurs, and a corresponding time delay introduced by each of the delay circuits may be based on a respective weighting factor applied to one or more samples of an output digital signal previously generated by the TB-DFE circuit. A phase detector may compare a timing of an edge of the delay data signal with a reference clock signal and generate the output digital signal based on the comparison.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 7, 2019
    Assignee: Regents of the University of Minnesota
    Inventors: Po-Wei Chiu, Somnath Kundu, Hyung-il Kim
  • Publication number: 20180351770
    Abstract: A time-based decision feedback equalizer (TB-DFE) circuit may include a voltage-to-time converter configured to convert a communication signal into a time-based signal. A timing of when an edge of the time-based signal occurs is indicative of a voltage level of the communication signal. The circuit may include a plurality of delay circuits arranged to process the time-based signal in series to generate a delay data signal. The delay circuits may adjust the timing of when the edge of the time-based signal occurs, and a corresponding time delay introduced by each of the delay circuits may be based on a respective weighting factor applied to one or more samples of an output digital signal previously generated by the TB-DFE circuit. A phase detector may compare a timing of an edge of the delay data signal with a reference clock signal and generate the output digital signal based on the comparison.
    Type: Application
    Filed: November 8, 2017
    Publication date: December 6, 2018
    Inventors: Po-Wei Chiu, Somnath Kundu, Hyung-il Kim
  • Patent number: 9379663
    Abstract: In one example, an oscillator circuit includes: a master oscillator comprising a master LC tank coupled to a master active circuit, the master LC tank including a primary winding of a transformer and a capacitance; a slave oscillator comprising a slave LC tank coupled to a slave active circuit, the slave LC tank including a secondary winding of the transformer and a capacitance; and a first pair of coupling transistors and a second pair of coupling transistors each coupling the master oscillator to the slave oscillator. Gates of the first pair of coupling transistors are coupled to the master oscillator through a switch. Gates of the second pair of coupling transistors are coupled to the master oscillator through respective ninety-degree phase shifters and the switch.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: June 28, 2016
    Assignee: XILINX, INC.
    Inventors: Somnath Kundu, Vassili Kireev
  • Patent number: 8183911
    Abstract: An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: May 22, 2012
    Assignee: STMicroelectronics International N.V.
    Inventors: Somnath Kundu, Pikul Sarkar, Nitin Gupta
  • Publication number: 20110090002
    Abstract: An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads.
    Type: Application
    Filed: October 19, 2009
    Publication date: April 21, 2011
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventors: Somnath Kundu, Pikul Sarkar, Nitin Gupta