Abstract: Devices, systems and methods are disclosed for readying a device from hibernation with reduced user-perceived latency. For example, data likely to be accessed may be selected as preload data that is loaded into volatile memory prior to the device resuming system interactivity (e.g., being responsive to user input), thus “anticipating” user demand by loading memory pages that the user will likely request. The device may determine additional data to add to the preload data based on processes running on the device and virtual memory areas (VMAs) associated with the processes, may weight the processes and may intelligently determine the data so that the device more rapidly reaches system interactivity.

Abstract: Devices, systems and methods are disclosed for limiting a number of hibernations based on a finite lifetime expectancy of nonvolatile memory. As the nonvolatile memory has a finite lifetime expectancy, a device may determine cumulative thresholds and associated session thresholds and may limit a frequency that the device hibernates. For example, the device may determine a cumulative number of hibernations and associate the cumulative number of hibernations with a cumulative threshold. The device may determine a session threshold corresponding to the cumulative threshold and may limit a number of hibernations using the session threshold. For example, the device may enter a hibernation state up to the session threshold and thereafter may enter a suspended state instead.

Abstract: One aspect of the invention provides a theft detection system including one or more tag nodes configured to detect movement and transmit a beacon message and one or more anchor nodes configured to receive the beacon message from the one or more tag nodes and alert a third party of the beacon message. Another aspect of the invention provides a theft detection node including a power source, a motion detector, a transmitter, and a microcontroller in communication with the power source, the motion detector, and the transmitter. The microcontroller is configured to determine whether the node is being transported and if the node is being transported, instructing the transmitter to transmit a beacon message. Another aspect of the invention provides a theft detection method including detecting motion in a motor vehicle and transmitting a beacon message to an anchor node.

Abstract: In one embodiment, a processor regularly writes one or more cache entries back to memory to reduce the likelihood of cache soft errors. The regularly occurring write backs operate independently of Least Recently Used (LRU) status of the entries so that all entries are flushed.

Abstract: An electronic device having logic that allows testing the device via a network interface is disclosed herein. The electronic device comprises the following. The electronic device has testing logic that receives test input signals and generate a test output signal. The electronic device has a network interface that is operable to receive network packets. The electronic device has packet processing logic communicatively coupled to the network interface that is able to determine whether a packet received in the network interface is a packet for testing the apparatus. The packet processing logic extracts test information from packets received on the network interface that are determined to be test packets, and generates the test input signals for the testing logic from the extracted test information. The packet processing logic incorporate test results into network packets based on the test output signal from the testing logic.

Abstract: In one embodiment, a Central Processing Unit having a processing core. The processing core connects to an internal memory bus having N address lines and X data lines. A cache connects to the internal memory bus and uses M of N bits of the N address lines to address data stored in the cache. A cryptographic unit in the CPU encrypts data written to an external memory and decrypts data read from the external memory. The cryptographic unit encrypts and decrypts N-M address lines of the internal memory bus and the data lines of the bus.

Abstract: A source endpoint connected via a Virtual Local Area Network to a first access port and a destination endpoint connected to a second access port. Two or more network processing devices indirectly connected through a backplane interconnect to transmit data between the source and destination endpoints according to a protected port status of the first and second access ports.

Abstract: An approach for improving a network management system by using a virtual machine in a network device is described. Applets are created and downloaded to the network device via flash memory or trivial file transfer protocol (“TFTP”). A loader environment in the virtual machine loads the applet for execution. The virtual machine converts the applet into machine code and executes said applet in said network device. This approach is supported by porting a virtual machine that executes a high level operating language to an operating system in a network device is described. A build process is executed wherein makefiles of the operating system and virtual machine are modified.

Abstract: In one embodiment, a processor regularly writes one or more cache entries back to memory to reduce the likelihood of cache soft errors. The regularly occurring write backs operate independently of Least Recently Used (LRU) status of the entries so that all entries are flushed.

Abstract: An electronic device having logic that allows testing the device via a network interface is disclosed herein. The electronic device comprises the following. The electronic device has testing logic that receives test input signals and generate a test output signal. The electronic device has a network interface that is operable to receive network packets. The electronic device has packet processing logic communicatively coupled to the network interface that is able to determine whether a packet received in the network interface is a packet for testing the apparatus. The packet processing logic extracts test information from packets received on the network interface that are determined to be test packets, and generates the test input signals for the testing logic from the extracted test information. The packet processing logic incorporate test results into network packets based on the test output signal from the testing logic.

Abstract: In one embodiment, a Central Processing Unit having a processing core. The processing core connects to an internal memory bus having N address lines and X data lines. A cache connects to the internal memory bus and uses M of N bits of the N address lines to address data stored in the cache. A cryptographic unit in the CPU encrypts data written to an external memory and decrypts data read from the external memory. The cryptographic unit encrypts and decrypts N-M address lines of the internal memory bus and the data lines of the bus.

Abstract: A source endpoint connected via a Virtual Local Area Network to a first access port and a destination endpoint connected to a second access port. Two or more network processing devices indirectly connected through a backplane interconnect to transmit data between the source and destination endpoints according to a protected port status of the first and second access ports.

Abstract: Methods and apparatus for achieving universal cross connect for Time Domain Modulated (TDM) data between a first and second data streams each having a corresponding time slot assignment are disclosed. Cross connect may be achieved through the use of a time slot assignment table.

Abstract: A method and apparatus for call-limiting one or more candidate calls received by a router is disclosed. The method and apparatus may be configured to determine whether ringing one or more candidate calls will exceed a predetermined power limit. If ringing the calls will not exceed said power limit, the calls may be forwarded. If ringing the calls will exceed the power limit, the calls may be placed in a queue.

Abstract: Method and apparatus for queuing packets are disclosed. In one aspect, a method may comprise assigning each packet a first value; dynamically assigning each packet a second value; and queuing each packet for transmission using the first and second values.

Abstract: An apparatus and method for supporting enhanced ring scheduling for devices on platforms with limited power supply while seeking to preserve caller ID information and normal ringing cadence is disclosed. The ring scheduling apparatus includes a “Line Manager” coupled to a “Ring Scheduler”. The Line manager monitors the signaling events and determines whether the signaling commands associated with the signaling events should be modified to indicate ringing, no ringing, or pass the signaling commands unmodified. The “Ring Scheduler” manages the available resources according to a ring cadence schedule so that the power supply of the device is not exceeded.