Patents by Inventor Somnath S. Nag

Somnath S. Nag has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit insulator and method
    Patent number: 6962883
    Abstract: A two-stage plasma enhance dielectric deposition with a first stage of low capacitively-coupled RF bias with conformal deposition (202) followed by high capacitively-coupled RF bias for planarizing deposition (204) limits the charge build up on the underlying structure (104, 106, 108).
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: November 8, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Somnath S. Nag, Girish A. Dixit, Srikanth Krishnan
  • Integrated circuit insulator and method
    Publication number: 20040259384
    Abstract: A two-stage plasma enhance dielectric deposition with a first stage of low capacitively-coupled RF bias with conformal deposition (202) followed by high capacitively-coupled RF bias for planarizing deposition (204) limits the charge build up on the underlying structure (104, 106, 108).
    Type: Application
    Filed: August 5, 2003
    Publication date: December 23, 2004
    Inventors: Somnath S. Nag, Girish A. Dixit, Srikanth Krishnan
  • Integration of fluorinated dielectrics in multi-level metallizations
    Patent number: 6424040
    Abstract: Deposition of titanium over fluoride-containing dielectrics requires the use of a method of passivation to prevent the formation of TiF4, which causes delamination of the metallization structure. Disclosed methods include the formation of layers of Al203, TiN, or Si3N4.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: July 23, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Somnath S. Nag, Changming Jin, Wei-Yung Hsu, Guoqiang Xing
  • Integrated circuit insulator and method
    Patent number: 6313010
    Abstract: A trench isolation structure including high density plasma enchanced silicon dioxide trench filling (122) with chemical mechanical polishing removal of non-trench oxide.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: November 6, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Somnath S. Nag, Amitava Chatterjee, Ih-Chin Chen
  • In-situ liner for isolation trench side walls and method
    Patent number: 6306725
    Abstract: An isolation trench (60) comprising a trench (20) formed in a semiconductor layer (12). A barrier layer (22) may be formed along the trench (20). A layer (50) of an insulation material may be formed over the barrier layer (22). A high density layer (55) of the insulation material may be formed in the trench (20) over the layer (50).
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: October 23, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Somnath S. Nag, Amitava Chatterjee
  • Air-bridge integration scheme for reducing interconnect delay
    Patent number: 6297125
    Abstract: Air-bridges are formed at controlled lateral separations using the extremely high HF etch rate of a gap-fill spin-on-glass such as uncured hydrogen silsequioxane (HSQ) in combination with other dielectrics having a much slower etch rate in HF. The advantages of an air-bridge system with controlled lateral separations include providing an interconnect isolation dielectric which meets all requirements for sub-0.5 micron technologies and providing a device with reduced reliability problems.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: October 2, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Somnath S. Nag, Amitava Chatterjee, Girish A. Dixit
  • Self-planarizing low-temperature doped-silicate-glass process capable of gap-filling narrow spaces
    Patent number: 6268297
    Abstract: A low-temperature pre-metal dielectric deposition process using phosphine-based chemistry in a high-density plasma chemical-vapor deposition technique. The process uses a phosphorous-doped oxide of up to 3.5 percent (wt) deposited at less than 350 degrees C. capable of filling 0.4 micron spaces between poly-silicon gates without microvoids.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: July 31, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Somnath S. Nag, Gregory B. Shinn, Girish A. Dixit
  • Process scheme to form controlled airgaps between interconnect lines to reduce capacitance
    Patent number: 6204200
    Abstract: A process for forming controlled airgaps (22) between metal lines (16). A two-step high density plasma (HDP) chemical vapor deposition (CVD) process is used to form the silicon dioxide dielectric layer (20) with the controlled airgaps (22). The first step involves a high gas flow and low substrate bias conditions to deposit silicon dioxide with a high deposition to sputter etch ratio. The second step uses a low gas flow and high substrate bias condition to increase the sputter component of the deposition.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: March 20, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Benjamin P. Shieh, Somnath S. Nag, Richard S. List
  • Protective liner for isolation trench side walls and method
    Patent number: 6143625
    Abstract: An isolation trench (60) may comprise a trench (20) formed in a semiconductor layer (12). A barrier layer (22) may be formed along the trench (20). A protective liner (50) may be formed over the barrier layer (22). The protective liner (50) may comprise a chemically deposited oxide. A high density layer of insulation material (55) may be formed in the trench (20) over the protective liner (50).
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: November 7, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Ih-Chin Chen, Amitava Chatterjee, Somnath S. Nag
  • Interlevel dielectrics with reduced dielectric constant
    Patent number: 6127285
    Abstract: A structure and method to further reduce the dielectric constant (capacitance) of high density plasma chemical vapor deposited silicon dioxide (SiO2 12). The dielectric constant of voids (i.e. air pockets) is close to k=1.0, and therefore the microvoids reduce the effective dielectric constant of the silicon dioxide 12. Use of HDPCVD conditions avoids residual hydrogen, which would degrade the dielectric constant.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: October 3, 2000
    Assignee: Dallas Instruments Incorporated
    Inventor: Somnath S. Nag