Abstract: A network device that controls the communication of data frames between stations includes a memory that stores frame pointers that point to addresses in an external memory. The data frames are stored in the external memory while the network device generates frame forwarding information for the respective data frames. The network device divides the available frame pointers into a number of categories corresponding to priorities associated with the data frames. When a frame is received at the network device, frame processing logic determines the priority of the data frame and checks whether a frame pointer corresponding to that particular priority is available. If no frame pointer corresponding to that priority is available, the multiport switch drops the data frame.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes network switch ports, each including a flow module configured for generating a packet signature based on layer 3 information within a received data packet. The flow module generates first and second hash keys according to a prescribed hashing function upon obtaining first and second portions of layer 3 information. The flow module combines the first and second hash keys to form the packet signature, and searches an on-chip signature table that indexes addresses of layer 3 switching entries by entry signatures, where the entry signatures are generated using the same prescribed hashing function on the first and second layer 3 portions of the layer 3 switching entries.

Abstract: The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The network interface offloads IPsec processing from the host processor. According to the invention, the security system includes two processors for encrypting and authenticating the outgoing data. Outgoing data packets are sent alternately to one or the other processor, whereby transmission processing can be accelerated relative to receive processing.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes network switch ports, each including a packet classifier module configured for generating a packet signature based on information within a received data packet and hash action values specified within a user-programmable template. In particular, the network switch stores a plurality of user-programmable templates, each configured for identifying a corresponding class of data packet. Each user-programmable template includes hash action values specifying initiation and termination of a hash function based on a byte offset of a received data packet.

Abstract: A network switch port includes a port filter configured to receive at least a portion of a data frame including layer 3 information and to generate a tag result. A queue block is configured for transferring the data frame to a buffer memory. A switch fabric is configured for receiving the tag result and for performing a frame forwarding switching decision based on the tag result and monitoring of the transfer of the data frame. A synchronizing device is configured to synchronize the transfer of a valid tag result to the switch fabric with the transfer of the at least a portion of the data frame to the buffer memory based on a signal from the queue indicating a status of the transfer of the portion of the data frame to the buffer memory.

Abstract: A multiport network device includes output ports, internal rules checking logic, a port filter, and input ports. The input ports receive data frames and transfer the data frames to the internal rules checking logic and the port filter. The internal rules checking logic determines the appropriate output ports for the frame. At potentially the same time, the port filter determines priority information for the frame. The port filter informs the internal rules checking logic when it has completed determining the priority information by transmitting an end-of-frame signal to the internal rules checking logic. In response, if the internal rules checking logic has completed determining the output ports for the frame, it assembles a frame descriptor corresponding to the frame and transmits the frame descriptor to the appropriate output port(s).

Abstract: A method is provided herein for use with a table containing a plurality of data entries, wherein each of the data entries consists of a string of data. Each data entry has a first address addressable by a first pointer from an upstream data entry and a second address addressable by a second pointer from an upstream data entry. Each data entry further includes a third pointer for addressing the address of a downstream data entry and a fourth pointer for addressing the address of a downstream data entry. In the present method, when it is detected, after a chosen interval of time, that a specified data entry has not been addressed by either of its addresses, the first and second pointers to that specified data entry are redirected to the destinations of the third and fourth pointers respectively. That specified data entry may then be deleted without compromise of the function of the table.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes network switch ports, each including a policy filter configured for obtaining layer 3 and layer 4 information from a received layer 2 frame. The layer 3 information and the layer 4 information is used to determine a policy identifier that specifies a layer 3 switching operation to be performed on the received layer 2 frame. Each network switch port also includes a flow identification module that caches portions of the layer 3 information and the corresponding policy identifier.

Abstract: A computer-based system is configured for generating a first data structure having entries representing respective network nodes having layer 2 and layer 3 network addresses. The system generates a second data structure, having a plurality of data packet headers, by selecting source and destination pairs from the first data structure and combining the respective layer 2 and layer 3 network addresses from the respective selected source and destination pairs with randomly-generated numbers representing layer 3 payload data. The second data structure is supplied to a switch model configured for parsing the layer 3 network addresses according to selected hash functions. Hence, the computer-based system is able to evaluate the selected hash functions based on a time-independent analysis, eliminating the necessity of building an actual network in hardware or simulating network traffic over a period of time.

Abstract: A centralized policy server sends policy messages, that describe network management policy, to network switches. Each policy message includes a packet attribute that enables a network switch to uniquely identify a received data packet, and either a priority level or network switch action that describes the switching operation to be performed by the network switch. The network switches are configured for implementing the network management policy by storing switching actions for prescribed data packets, and templates that specify frame data parameters for identifying the prescribed data packets. Each network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes in each network switch port a packet classifier module configured for classifying a received data packet based on a template generated based on the policy messages.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes network switch ports, each including a policy filter configured for obtaining layer 3 and layer 4 information from a received layer 2 frame. The layer 3 information and the layer 4 information are used to determine a policy identifier that specifies a layer 3 switching operation to be performed on the received layer 2 frame. Each network switch port also includes a policy cache that caches portions of the layer 3 information and the corresponding policy identifier. The policy filter and the policy cache are then simultaneously searched for subsequent layer 3 frames to find the appropriate policy; if the appropriate policy is located in the policy cache, the searching operation is completed, enabling the network switch port resources to begin searching operations for another packet.

Abstract: An integrated multiport switch will determine whether packets received at designated VLAN ports are tagged packets. If so, the VLAN tag is stripped from the packet before further processing the incoming data at the media access controller of the port. The stripped tag is forwarded to a rules checker, which determines further routing of the packet to one or more destinations. The VLAN tag data, which may be modified by the rules checker, and the remainder of the packet data are stored separately in a memory external to the integrated switch. A control register contains designated VLAN types that can be compared with the VLAN type field in the tagged packet. The number of bytes of data received can thus be counted to locate the field of the VLAN packet assigned to VLAN type. VLAN tags may be readily inserted in untagged or stripped packets that are to be transmitted at a VLAN port.

Abstract: A multiport data network switch with each port associated with a media access controller (MAC) that is allocated a time slot in a repetitive sequence of clock cycles. A random number generator is coupled in common to each MAC to output a random number signal thereto. In response to a collision indicating signal, received at a port during a data transmission, the MAC outputs a retransmission retry signal in accordance with the random number signal that represents a number of delay cycles in which said transmission is delayed. The random number signal generator outputs an increasing multibit signal that is periodically reset. The MAC associated with each port is coupled in common to the shared random number signal generator and gains access thereto at a different respective time slot.

Abstract: An integrated multiport switch (IMS) in which one combinational logic and register arrangement is provided for executing similar media access control (MAC) functions for a plurality of switch ports. The current access state at each of a plurality of switch ports is maintained at a single state storage location, whereby access of a stored port MAC state and update thereof is simplified. Access to state storage in coordination with the single common combinational logic and register arrangement enables MAC functions for each of the plurality of ports to be performed on a time shared basis to maximize efficiency of use of chip resources and architecture space.

Abstract: An arrangement for designing a testing modeling system provides a testing hierarchy, where non-standard device elements having internal memory and logic structures are modeled by partitioning the device element into a recognizable memory model and a recognizable logic model separate from the memory model. The segregated models are then verified for accuracy using existing design and simulation tool and with comparison to existing hardware implementations. Once the revised models have been verified, the new models can be stored in a model library for future use.

Abstract: A network switch having multiple media access control (MAC) switch ports has a physical transceiver interface that generates a time-division multiplexed serial data stream and outputs the time-division multiplexed serial data stream to a physical layer transceiver serving a respective multiple number of network nodes. The physical transceiver interface is also configured for receiving a time-division multiplexed serial input stream from the physical transceiver according to another repeating sequence of time slots corresponding to the network switch ports, where each of the serial data streams between the physical transceiver interface and the physical layer transceiver are synchronized relative to a shared system clock and a shared reset signal.