Patents by Inventor Somnuk Ratanaphanyarat
Somnuk Ratanaphanyarat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6151200Abstract: Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.Type: GrantFiled: December 2, 1999Date of Patent: November 21, 2000Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Jente B. Kuang, Somnuk Ratanaphanyarat, Mary J. Saccamango
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Patent number: 6078058Abstract: Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.Type: GrantFiled: March 5, 1998Date of Patent: June 20, 2000Assignee: International Business Machine CorporationInventors: Louis L. Hsu, Jente B. Kuang, Somnuk Ratanaphanyarat, Mary J. Saccamango
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Patent number: 5874764Abstract: An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.Type: GrantFiled: July 24, 1996Date of Patent: February 23, 1999Assignee: International Business Machines CorporationInventors: Chang-Ming Hsieh, Somnuk Ratanaphanyarat, Shao-Fu Sanford Chu, Louis Lu-chen Hsu
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Patent number: 5872733Abstract: An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current. In one embodiment, the apparatus comprises a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output. The body is adapted for connection to the charge pump output. The apparatus further comprises a control circuit having an input adapted for connection to the charge pump output and an output connected to the bleeder circuit input. The control circuit provides a voltage potential to the input of the current bleeder circuit to control the gate-to-source voltage of the current bleeder circuit transistor.Type: GrantFiled: October 21, 1996Date of Patent: February 16, 1999Assignee: International Business Machines CorporationInventors: Taqi Nasser Buti, Louis Lu-Chen Hsu, Jente B. Kuang, Somnuk Ratanaphanyarat, Mary Joseph Saccamango, Hyun Jong Shin
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Patent number: 5736891Abstract: A discharge circuit for a semiconductor memory includes a first node, a second node for receiving a control signal having first and second states, and a circuit connected between the first node and ground potential and to the second node. The circuit couples the first node to ground potential when the control signal has the first state and substantially isolates the first node from ground potential when the control signal has the second state. The circuit includes a first subcircuit for defining a current path between the first node and ground potential. The first subcircuit includes a plurality of transistors connected in series, each of which having a gate, source and drain. The circuit further includes a second subcircuit for effecting predetermined gate-to-source, and drain-to-source voltages of the transistors of the first subcircuit when the control signal has the second state.Type: GrantFiled: January 11, 1996Date of Patent: April 7, 1998Assignee: International Business Machines CorporationInventors: Taqi Nasser Buti, Louis Lu-Chen Hsu, Jente B. Kuang, Somnuk Ratanaphanyarat, Mary J. Saccamango, Hyun Jong Shin
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Patent number: 5721485Abstract: High performance on-chip voltage regulator designs are disclosed which have settling times which are fast enough to meet today's microprocessor/microcontroller requirements when they are entering an active mode from a passive mode. A first preferred embodiment provides a circuit in which a single pulse control signal is required to instantly raise Vy when the microprocessor is in the wake-up period. The circuit includes a charge pump, a differential amplifier, and a microprocessor connected to the power supply through a voltage regulating device. A second embodiment provides a circuit to stimulate Vint prior to CPU wake-up. The principle of operation of this embodiment is to stimulate the voltage regulating device prior to CPU wake-up. By stimulating (pulling down) the Vint node, the voltage regulating device will raise Vy and ready the microprocessor to draw a large current.Type: GrantFiled: January 4, 1996Date of Patent: February 24, 1998Assignee: IBM CorporationInventors: Louis Lu-Chen Hsu, Toshiaki Kirihata, Somnuk Ratanaphanyarat, Hyun Jong Shin
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Patent number: 5721144Abstract: An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.Type: GrantFiled: October 24, 1995Date of Patent: February 24, 1998Assignee: International Business Machines CorporationInventors: Chang-Ming Hsieh, Somnuk Ratanaphanyarat, Shao-Fu Sanford Chu, Louis Lu-chen Hsu
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Patent number: 5331199Abstract: A vertical bipolar transistor is constructed with reduced step height by codeposition of a polysilicon base contact member and an epitaxial device layer, thereby placing the base contact below the device surface, and by the use of a doped glass layer as a dopant source for the base contact and as a dopant source to provide a continuous conductive path to the base, and as the dielectric separating the base contact from the emitter contact, and as an etch stop when forming the base implantation aperture.Type: GrantFiled: April 16, 1993Date of Patent: July 19, 1994Assignee: International Business Machines CorporationInventors: Shao-Fu S. Chu, Kyong-Min Kim, Shaw-Ning Mei, Victor R. Nastasi, Somnuk Ratanaphanyarat
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Patent number: 5286334Abstract: A method of depositing Ge on a Si substrate in a reaction chamber includes the steps of: precleaning the substrate; evacuating the chamber to a pressure below 10.sup.-7 Torr; heating the substrate to 300.degree.-600.degree. C.; and providing a GeH.sub.4 /B.sub.2 H.sub.6 /He mixture of gas with a GeH.sub.4 partial pressure of 2-50 mTorr and a B.sub.2 H.sub.6 partial pressure of 0.08 to 2 mTorr.Type: GrantFiled: October 21, 1991Date of Patent: February 15, 1994Assignee: International Business Machines CorporationInventors: Shahzad Akbar, Jack O. Chu, Brian Cunningham, Gregory Fitzgibbon, Somnuk Ratanaphanyarat
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Patent number: 5234846Abstract: A vertical bipolar transistor is constructed with reduced step height by codeposition of a polysilicon base contact member and an epitaxial device layer, thereby placing the base contact below the device surface, and by the use of a doped glass layer as a dopant source for the base contact and as a dopant source to provide a continuous conductive path to the base, and as the dielectric separating the base contact from the emitter contact, and as an etch stop when forming the base implantation aperture.Type: GrantFiled: April 30, 1992Date of Patent: August 10, 1993Assignee: International Business Machines CorporationInventors: Shao-Fu S. Chu, Kyong-Min Kim, Mei Shaw-Ning, Victor R. Nastasi, Somnuk Ratanaphanyarat