Patents by Inventor Somvir Dahiya

Somvir Dahiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10045366
    Abstract: An eNode-B includes PUSH mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. A buffer receives and stores first and second identifiers. A de-multiplexer outputs a first code word number based on the first identifier and a second code word number based on the second identifier. A set of completion queues store the first and second code word numbers. A sequence controller generates first and second select signals corresponding to the first and second identifiers. A multiplexer outputs one of the first and second code word numbers based on the select signals, and the scheduler schedules the first and second code words based on the first and second identifiers.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: August 7, 2018
    Assignee: NXP USA, INC.
    Inventors: Somvir Dahiya, Arvind Kaushik, Aviel Livay, Amrit P. Singh
  • Publication number: 20180020468
    Abstract: An eNode-B includes PUSH mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. A buffer receives and stores first and second identifiers. A de-multiplexer outputs a first code word number based on the first identifier and a second code word number based on the second identifier. A set of completion queues store the first and second code word numbers. A sequence controller generates first and second select signals corresponding to the first and second identifiers. A multiplexer outputs one of the first and second code word numbers based on the select signals, and the scheduler schedules the first and second code words based on the first and second identifiers.
    Type: Application
    Filed: July 18, 2016
    Publication date: January 18, 2018
    Inventors: SOMVIR DAHIYA, ARVIND KAUSHIK, AVIEL LIVAY, AMRIT P. SINGH
  • Patent number: 9785368
    Abstract: A system for mapping control and user data includes a direction scanner, an address calculator, a collision detector, a buffer, and a mapper for mapping control and user data from a first memory to a second memory. The direction scanner determines the highest priority value of to a code word index. The address calculator calculates start and end addresses of the highest priority value. When an address from an address range, defined by the start and end addresses, is already mapped to other control data, the collision detector detects a collision and generates feedback data. The address calculator outputs modified start and end addresses based on the feedback data. When no collision is detected, the address calculator outputs the modified start and end addresses to the buffer. The mapper then maps the control and user data to the modified start and end addresses in the second memory.
    Type: Grant
    Filed: July 24, 2016
    Date of Patent: October 10, 2017
    Assignee: NXP USA, INC.
    Inventors: Ritika Sharma, Somvir Dahiya, Arvind Kaushik, Amrit P. Singh
  • Patent number: 9788314
    Abstract: A base transceiver station (BTS) includes dedicated memories to store uplink real-time (RT) data received by way of an antenna of the BTS and downlink RT data generated by processors of the BTS. The dedicated memories serve a dedicated number of processors, which prevents over-run and under-run of antenna buffers and provides deterministic data flow necessary to stream time-critical uplink and downlink RT data. Thus, a high and dedicated bandwidth for the uplink and downlink RT data is ensured.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: October 10, 2017
    Assignee: NXP USA, INC.
    Inventors: Girraj K. Agrawal, Somvir Dahiya, Rajan Kapoor, Arvind Kaushik, Vincent Martinez
  • Publication number: 20170164333
    Abstract: A base transceiver station (BTS) includes dedicated memories to store uplink real-time (RT) data received by way of an antenna of the BTS and downlink RT data generated by processors of the BTS. The dedicated memories serve a dedicated number of processors, which prevents over-run and under-run of antenna buffers and provides deterministic data flow necessary to stream time-critical uplink and downlink RT data. Thus, a high and dedicated bandwidth for the uplink and downlink RT data is ensured.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 8, 2017
    Inventors: Girraj K. Agrawal, Somvir Dahiya, Rajan Kapoor, Arvind Kaushik, Vincent Martinez
  • Patent number: 9661521
    Abstract: A system for merging first and second interrupts includes first and second queue modules, first and second status modules, and first and second merger modules. The first and second queue modules receive first and second en-queue signals corresponding to the first and second interrupts, first and second de-queue signals, and generate first and second status signals. The first and second status modules receive first and second status signals, and first and second output signals, and generate first and second merge signals. The first and second merger modules receive the first and second merge signals, and generate the first and second output signals. One of the first and second output signals is indicative of the first and second en-queue signals, thereby merging the first and second interrupts into at least one of the first and second output signals.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: May 23, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Somvir Dahiya, Rajan Kapoor, Arvind Kaushik
  • Publication number: 20160205583
    Abstract: A system for merging first and second interrupts includes first and second queue modules, first and second status modules, and first and second merger modules. The first and second queue modules receive first and second en-queue signals corresponding to the first and second interrupts, first and second de-queue signals, and generate first and second status signals. The first and second status modules receive first and second status signals, and first and second output signals, and generate first and second merge signals. The first and second merger modules receive the first and second merge signals, and generate the first and second output signals. One of the first and second output signals is indicative of the first and second en-queue signals, thereby merging the first and second interrupts into at least one of the first and second output signals.
    Type: Application
    Filed: January 8, 2015
    Publication date: July 14, 2016
    Inventors: Somvir Dahiya, Rajan Kapoor, Arvind Kaushik
  • Patent number: 9392640
    Abstract: A method and apparatus automatically controls the insertion of information flow data over a shared CPRI link (561) by providing a hardware control mechanism (504-509) at a local radio base station subsystem (501) connected in a CPRI daisy chain configuration between a downstream RE device (570) and an upstream REC device (560) for determining whether the control word being transmitted is sourced from a downstream device (e.g., forwarded data from a downstream RE device) or from the local device.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: July 12, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tuongvu V. Nguyen, John J. Vaglica, Roy Shor, Somvir Dahiya, Ori Goren, Avraham Horn, Arvind Kaushik, Arindam Sinha, Puneet Wadhawan
  • Patent number: 9380473
    Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a transmission configuration. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in various transmission configurations.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: June 28, 2016
    Assignee: FREESCALE SEMICONDUCTOR,INC.
    Inventors: Somvir Dahiya, Nikhil Jain, Rajan Kapoor
  • Patent number: 9332567
    Abstract: An integrated circuit (IC) in an unresponsive radio equipment (RE) node includes a common public radio interface (CPRI) controller, a processor, and a system reset controller that includes an L1 (Layer 1) reset controller. The CPRI controller generates a reset request signal based on a CPRI reset request received from an RE controller (REC). The L1 reset controller generates a traffic stop signal based on the reset request signal. The CPRI controller generates a traffic idle signal based on the traffic stop signal. The L1 reset controller receives the traffic idle signal before a predetermined time period and generates a system reset signal for resetting the processor, thereby recovering the unresponsive RE node without disrupting the network topology of a communication system that includes the REC and multiple RE nodes including the unresponsive RE node connected via a CPRI link.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: May 3, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Inayat Ali, Somvir Dahiya, Arvind Kaushik, Sachin Prakash
  • Publication number: 20150350927
    Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a transmission configuration. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in various transmission configurations.
    Type: Application
    Filed: May 27, 2014
    Publication date: December 3, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Somvir Dahiya, Nikhil Jain, Rajan Kapoor
  • Patent number: 9204312
    Abstract: Adding a new subsystem node to a multi-node base station topology (e.g., a chain or tree topology) in a telecommunications network can disrupt the effective operation of the existing multi-node base station. By accurately measuring the timing difference between uplink and downlink signaling across a current terminating node during the configuration of the new terminating node, the new node can be added with reduced impact upon the operation of the existing base station nodes.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: December 1, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Arindam Sinha, Somvir Dahiya, Arvind Garg, Sachin Jain, Arvind Kaushik
  • Patent number: 9088941
    Abstract: A transmission node for use in a wireless communication network includes a first CPRI unit for transmitting auxiliary data to a second CPRI unit in the transmission node. A memory unit stores control word data of the auxiliary data. A memory write block is connected between the first CPRI unit and the memory unit for writing the control word data to the memory unit based on a first set of frame timing signals received from the first CPRI unit. A memory read and merge block is connected to the memory unit for reading the control word data stored in the memory unit based on a second set of frame timing signals, merging the control word data with IQ data, and transmitting the merged auxiliary data to the second CPRI unit.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: July 21, 2015
    Assignee: FREESCALE SEMICONDUCTOR,INC
    Inventors: Arvind Garg, Somvir Dahiya, Sachin Jain, Arvind Kaushik, Arindam Sinha
  • Publication number: 20150146626
    Abstract: Adding a new subsystem node to a multi-node base station topology (e.g., a chain or tree topology) in a telecommunications network can disrupt the effective operation of the existing multi-node base station. By accurately measuring the timing difference between uplink and downlink signaling across a current terminating node during the configuration of the new terminating node, the new node can be added with reduced impact upon the operation of the existing base station nodes.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Inventors: Arindam Sinha, Somvir Dahiya, Arvind Garg, Sachin Jain, Arvind Kaushik
  • Patent number: 9031056
    Abstract: A transmission node for use in a wireless communication network includes a first register for storing a set of first mask bits, a second register for storing a set of second mask bits, and a mask switching block for multiplexing the set of first mask bits and the set of second mask bits and outputting the set of third mask bits. The transmission node further includes a CPRI unit with an auxiliary interface for receiving the set of third mask bits. An activation block is connected between the CPRI unit and the mask switching block for causing the mask switching block to output the set of second mask bits based on data in a current frame in the CPRI unit.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: May 12, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sachin Jain, Somvir Dahiya, Arvind Garg, Arvind Kaushik, Arindam Sinha
  • Publication number: 20150016445
    Abstract: A transmission node for use in a wireless communication network includes a first CPRI unit for transmitting auxiliary data to a second CPRI unit in the transmission node. A memory unit stores control word data of the auxiliary data. A memory write block is connected between the first CPRI unit and the memory unit for writing the control word data to the memory unit based on a first set of frame timing signals received from the first CPRI unit. A memory read and merge block is connected to the memory unit for reading the control word data stored in the memory unit based on a second set of frame timing signals, merging the control word data with IQ data, and transmitting the merged auxiliary data to the second CPRI unit.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 15, 2015
    Inventors: Arvind Garg, Somvir Dahiya, Sachin Jain, Arvind Kaushik, Arindam Sinha
  • Publication number: 20150016444
    Abstract: A transmission node for use in a wireless communication network includes a first register for storing a set of first mask bits, a second register for storing a set of second mask bits, and a mask switching block for multiplexing the set of first mask bits and the set of second mask bits and outputting the set of third mask bits. The transmission node further includes a CPRI unit with an auxiliary interface for receiving the set of third mask bits. An activation block is connected between the CPRI unit and the mask switching block for causing the mask switching block to output the set of second mask bits based on data in a current frame in the CPRI unit.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 15, 2015
    Inventors: Sachin Jain, Somvir Dahiya, Arvind Garg, Arvind Kaushik, Arindam Sinha
  • Patent number: 8873466
    Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a cellular network. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in multiple cellular networks.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: October 28, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Asif Iqbal, Somvir Dahiya, Nikhil Jain, Rajan Kapoor, Saleem Mohamedali
  • Publication number: 20140105185
    Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a cellular network. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in multiple cellular networks.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Asif Iqbal, Somvir Dahiya, Nikhil Jain, Rajan Kapoor, Saleem Mohamedali
  • Publication number: 20140094157
    Abstract: A method and apparatus automatically controls the insertion of information flow data over a shared CPRI link (561) by providing a hardware control mechanism (504-509) at a local radio base station subsystem (501) connected in a CPRI daisy chain configuration between a downstream RE device (570) and an upstream REC device (560) for determining whether the control word being transmitted is sourced from a downstream device (e.g., forwarded data from a downstream RE device) or from the local device.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 3, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tuongvu V. Nguyen, John J. Vaglica, Roy Shor, Somvir Dahiya, Ori Goren, Avraham Horn, Arvind Kaushik, Arindam Sinha, Puneet Wadhawan