Patents by Inventor Son T. Dao

Son T. Dao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10846054
    Abstract: Methods and apparatuses for generating a condition code for a floating point number operation prior to normalization. A processor receives an intermediate result for an operation, wherein the intermediate result comprises an intermediate significand and an intermediate exponent. A processor determines a mask based on the value of the intermediate exponent. A processor generates a masked significand by applying the mask to the intermediate significand. A processor generates a condition code based on the masked significand having a predetermined value.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: November 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Son T. Dao, Silvia Melitta Mueller
  • Patent number: 10846053
    Abstract: Methods and apparatuses for generating a condition code for a floating point number operation prior to normalization. A processor receives an intermediate result for an operation, wherein the intermediate result comprises an intermediate significand and an intermediate exponent. A processor determines a mask based on the value of the intermediate exponent. A processor generates a masked significand by applying the mask to the intermediate significand. A processor generates a condition code based on the masked significand having a predetermined value.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: November 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Son T. Dao, Silvia Melitta Mueller
  • Patent number: 10489114
    Abstract: Methods and apparatuses for performing a floating point multiply-add operation with alignment correction. A processor receives a first operand, a second operand and a third operand, wherein the first, second and third operands each represent a floating point number comprising a significand value and a biased exponent value. A processor determines a shift amount based, at least in part, on the one or more biased exponent values of the first, second or third operand. A processor determines a shift amount correction based, at least in part, on the one or more biased exponent values of the first, second or third operand being equal to zero.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Son T. Dao, Silvia Melitta Mueller
  • Patent number: 10489115
    Abstract: Methods and apparatuses for performing a floating point multiply-add operation with alignment correction. A processor receives a first operand, a second operand and a third operand, wherein the first, second and third operands each represent a floating point number comprising a significand value and a biased exponent value. A processor determines a shift amount based, at least in part, on the one or more biased exponent values of the first, second or third operand. A processor determines a shift amount correction based, at least in part, on the one or more biased exponent values of the first, second or third operand being equal to zero.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Son T. Dao, Silvia Melitta Mueller
  • Patent number: 10379860
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Patent number: 10379859
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Publication number: 20170235573
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Publication number: 20170235574
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Patent number: 9684514
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Patent number: 9684515
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Patent number: 9529664
    Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: December 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Son T. Dao, Juergen Haess, Michael Klein, Silvia M. Mueller
  • Publication number: 20160357636
    Abstract: Software that provides a subset of error correcting code (ECC) bits to be used for parity purposes. The software performs the following steps: (i) providing, in a data block, a first set of redundant bits adapted to detect and correct errors in the data block, based, at least in part, on a first set of error detection/correction (EDC) requirements; and (ii) providing, within the first set of redundant bits, a first sub-set of parity bit(s) adapted to provide single bit error detection for the data block. The EDC requirements include: (i) a minimum hamming distance, and (ii) the bit(s) in the first set of redundant bits that are not in the first sub-set of parity bit(s) include enough bit(s) to create at least P unique (M-2)-tuples, where P equals the number of bits in the first sub-set of parity bits, and where M equals the minimum hamming distance.
    Type: Application
    Filed: August 17, 2016
    Publication date: December 8, 2016
    Inventors: Son T. Dao, Juergen Haess, Michael Klein, Silvia M. Mueller
  • Patent number: 9513987
    Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Son T. Dao, Juergen Haess, Michael Klein, Silvia M. Mueller
  • Publication number: 20160132385
    Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.
    Type: Application
    Filed: December 19, 2014
    Publication date: May 12, 2016
    Inventors: Son T. Dao, Juergen Haess, Michael Klein, Silvia M. Mueller
  • Publication number: 20160132390
    Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 12, 2016
    Inventors: Son T. Dao, Juergen Haess, Michael Klein, Silvia M. Mueller
  • Publication number: 20160070572
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 10, 2016
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Publication number: 20160070573
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Application
    Filed: October 15, 2014
    Publication date: March 10, 2016
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Publication number: 20150378678
    Abstract: Methods and apparatuses for performing a floating point multiply-add operation with alignment correction. A processor receives a first operand, a second operand and a third operand, wherein the first, second and third operands each represent a floating point number comprising a significand value and a biased exponent value. A processor determines a shift amount based, at least in part, on the one or more biased exponent values of the first, second or third operand. A processor determines a shift amount correction based, at least in part, on the one or more biased exponent values of the first, second or third operand being equal to zero.
    Type: Application
    Filed: December 17, 2014
    Publication date: December 31, 2015
    Inventors: Son T. Dao, Silvia Melitta Mueller
  • Publication number: 20150378677
    Abstract: Methods and apparatuses for performing a floating point multiply-add operation with alignment correction. A processor receives a first operand, a second operand and a third operand, wherein the first, second and third operands each represent a floating point number comprising a significand value and a biased exponent value. A processor determines a shift amount based, at least in part, on the one or more biased exponent values of the first, second or third operand. A processor determines a shift amount correction based, at least in part, on the one or more biased exponent values of the first, second or third operand being equal to zero.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventors: Son T. Dao, Silvia Melitta Mueller
  • Publication number: 20150378680
    Abstract: Methods and apparatuses for generating a condition code for a floating point number operation prior to normalization. A processor receives an intermediate result for an operation, wherein the intermediate result comprises an intermediate significand and an intermediate exponent. A processor determines a mask based on the value of the intermediate exponent. A processor generates a masked significand by applying the mask to the intermediate significand. A processor generates a condition code based on the masked significand having a predetermined value.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventors: Son T. Dao, Silvia Melitta Mueller