Patents by Inventor Son T. Dao
Son T. Dao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10846053Abstract: Methods and apparatuses for generating a condition code for a floating point number operation prior to normalization. A processor receives an intermediate result for an operation, wherein the intermediate result comprises an intermediate significand and an intermediate exponent. A processor determines a mask based on the value of the intermediate exponent. A processor generates a masked significand by applying the mask to the intermediate significand. A processor generates a condition code based on the masked significand having a predetermined value.Type: GrantFiled: June 27, 2014Date of Patent: November 24, 2020Assignee: International Business Machines CorporationInventors: Son T. Dao, Silvia Melitta Mueller
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Patent number: 10846054Abstract: Methods and apparatuses for generating a condition code for a floating point number operation prior to normalization. A processor receives an intermediate result for an operation, wherein the intermediate result comprises an intermediate significand and an intermediate exponent. A processor determines a mask based on the value of the intermediate exponent. A processor generates a masked significand by applying the mask to the intermediate significand. A processor generates a condition code based on the masked significand having a predetermined value.Type: GrantFiled: December 17, 2014Date of Patent: November 24, 2020Assignee: International Business Machines CorporationInventors: Son T. Dao, Silvia Melitta Mueller
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Patent number: 10489115Abstract: Methods and apparatuses for performing a floating point multiply-add operation with alignment correction. A processor receives a first operand, a second operand and a third operand, wherein the first, second and third operands each represent a floating point number comprising a significand value and a biased exponent value. A processor determines a shift amount based, at least in part, on the one or more biased exponent values of the first, second or third operand. A processor determines a shift amount correction based, at least in part, on the one or more biased exponent values of the first, second or third operand being equal to zero.Type: GrantFiled: December 17, 2014Date of Patent: November 26, 2019Assignee: International Business Machines CorporationInventors: Son T. Dao, Silvia Melitta Mueller
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Patent number: 10489114Abstract: Methods and apparatuses for performing a floating point multiply-add operation with alignment correction. A processor receives a first operand, a second operand and a third operand, wherein the first, second and third operands each represent a floating point number comprising a significand value and a biased exponent value. A processor determines a shift amount based, at least in part, on the one or more biased exponent values of the first, second or third operand. A processor determines a shift amount correction based, at least in part, on the one or more biased exponent values of the first, second or third operand being equal to zero.Type: GrantFiled: June 27, 2014Date of Patent: November 26, 2019Assignee: International Business Machines CorporationInventors: Son T. Dao, Silvia Melitta Mueller
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Patent number: 10379859Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: GrantFiled: May 3, 2017Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Patent number: 10379860Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: GrantFiled: May 3, 2017Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Publication number: 20170235573Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: ApplicationFiled: May 3, 2017Publication date: August 17, 2017Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Publication number: 20170235574Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: ApplicationFiled: May 3, 2017Publication date: August 17, 2017Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Patent number: 9684514Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: GrantFiled: September 10, 2014Date of Patent: June 20, 2017Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Patent number: 9684515Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: GrantFiled: October 15, 2014Date of Patent: June 20, 2017Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Patent number: 9529664Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.Type: GrantFiled: December 19, 2014Date of Patent: December 27, 2016Assignee: International Business Machines CorporationInventors: Son T. Dao, Juergen Haess, Michael Klein, Silvia M. Mueller
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Publication number: 20160357636Abstract: Software that provides a subset of error correcting code (ECC) bits to be used for parity purposes. The software performs the following steps: (i) providing, in a data block, a first set of redundant bits adapted to detect and correct errors in the data block, based, at least in part, on a first set of error detection/correction (EDC) requirements; and (ii) providing, within the first set of redundant bits, a first sub-set of parity bit(s) adapted to provide single bit error detection for the data block. The EDC requirements include: (i) a minimum hamming distance, and (ii) the bit(s) in the first set of redundant bits that are not in the first sub-set of parity bit(s) include enough bit(s) to create at least P unique (M-2)-tuples, where P equals the number of bits in the first sub-set of parity bits, and where M equals the minimum hamming distance.Type: ApplicationFiled: August 17, 2016Publication date: December 8, 2016Inventors: Son T. Dao, Juergen Haess, Michael Klein, Silvia M. Mueller
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Patent number: 9513987Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.Type: GrantFiled: November 7, 2014Date of Patent: December 6, 2016Assignee: International Business Machines CorporationInventors: Son T. Dao, Juergen Haess, Michael Klein, Silvia M. Mueller
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Publication number: 20160132390Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.Type: ApplicationFiled: November 7, 2014Publication date: May 12, 2016Inventors: Son T. Dao, Juergen Haess, Michael Klein, Silvia M. Mueller
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Publication number: 20160132385Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.Type: ApplicationFiled: December 19, 2014Publication date: May 12, 2016Inventors: Son T. Dao, Juergen Haess, Michael Klein, Silvia M. Mueller
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Publication number: 20160070572Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: ApplicationFiled: September 10, 2014Publication date: March 10, 2016Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Publication number: 20160070573Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: ApplicationFiled: October 15, 2014Publication date: March 10, 2016Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Publication number: 20150378678Abstract: Methods and apparatuses for performing a floating point multiply-add operation with alignment correction. A processor receives a first operand, a second operand and a third operand, wherein the first, second and third operands each represent a floating point number comprising a significand value and a biased exponent value. A processor determines a shift amount based, at least in part, on the one or more biased exponent values of the first, second or third operand. A processor determines a shift amount correction based, at least in part, on the one or more biased exponent values of the first, second or third operand being equal to zero.Type: ApplicationFiled: December 17, 2014Publication date: December 31, 2015Inventors: Son T. Dao, Silvia Melitta Mueller
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Publication number: 20150378677Abstract: Methods and apparatuses for performing a floating point multiply-add operation with alignment correction. A processor receives a first operand, a second operand and a third operand, wherein the first, second and third operands each represent a floating point number comprising a significand value and a biased exponent value. A processor determines a shift amount based, at least in part, on the one or more biased exponent values of the first, second or third operand. A processor determines a shift amount correction based, at least in part, on the one or more biased exponent values of the first, second or third operand being equal to zero.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Inventors: Son T. Dao, Silvia Melitta Mueller
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Publication number: 20150378680Abstract: Methods and apparatuses for generating a condition code for a floating point number operation prior to normalization. A processor receives an intermediate result for an operation, wherein the intermediate result comprises an intermediate significand and an intermediate exponent. A processor determines a mask based on the value of the intermediate exponent. A processor generates a masked significand by applying the mask to the intermediate significand. A processor generates a condition code based on the masked significand having a predetermined value.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Inventors: Son T. Dao, Silvia Melitta Mueller