Patents by Inventor Sonal Rattnam Sarthi

Sonal Rattnam Sarthi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10212599
    Abstract: An electronic slave device that provides one or more services to master devices, can be registered with a single true-owner device and one or more co-owner devices. The true-owner device can set independent permissions for the slave device's services as being free (all can use), restricted (only true-owner and co-owners can use), or locked (only true-owner can use), and hide locked services from non-owner devices. In one commerce mode, the slave device is sold with the true-owner device. In another commerce mode, the slave device is sold separately and the initially requesting master device can be the true-owner device.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: February 19, 2019
    Assignee: NXP B.V.
    Inventor: Sonal Rattnam Sarthi
  • Publication number: 20110018595
    Abstract: A metastability hardened synchronizer circuit includes a plurality of transmission gates, each transmission gate responsive to an input signal and a clock signal to generate a driver signal. The synchronizer circuit also includes a plurality of latches. The plurality of latches includes a first one of the latches in electrical communication with any one of the plurality of transmission gates and responsive to a driver signal to resolve to a stable state and a second one of the latches in electrical communication with another transmission gate of the plurality of transmission gates and responsive to another driver signal to resolve to the stable state.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 27, 2011
    Applicant: Texas Instruments Incorporated
    Inventor: Sonal Rattnam SARTHI
  • Patent number: 7825689
    Abstract: An exemplary functional input sequential circuit for reducing the setup time of input signals. The functional sequential circuit includes a tri-state inverter having an input signal and two control signals. The transmission circuit receives a control signal from a combinational logic circuit that performs a logical operation on a second input signal and a clock signal. The output of the transmission circuit is coupled to a digital storage element. Further, a control circuit is coupled to the digital storage element in order to force a value on the digital storage element when no input signal is received from the transmission circuit. The control circuit is also controlled by the second input signal and a clock signal.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: November 2, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Mahesh Ramdas Vasishta, Pavan Vithal Torvi, Sonal Rattnam Sarthi, Badarish Mohan Subbannavar