Abstract: The present invention provides a process for forming inlaid patterns of metal into specified areas of a patterned substrate. The process, which is useful in the manufacture of semiconductor devices and circuits, comprises selectively removing seed layer from all surfaces save the trenches and vias and selectively electroless plating a metal into the patterned substrate where the seed layer remains. The present invention further provides an abrasive-free polishing-pad configured to planarize a metal plated surface, agitate chemical reagents and facilitate removal of gases generated by the electroless plating process.