Patents by Inventor Soner Yaldiz
Soner Yaldiz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9800251Abstract: A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.Type: GrantFiled: October 9, 2015Date of Patent: October 24, 2017Assignee: International Business Machines CorporationInventors: Mark Ferriss, Arun S. Natarajan, Benjamin D. Parker, Alexander V. Rylyakov, Jose A. Tierno, Soner Yaldiz
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Publication number: 20160036452Abstract: A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.Type: ApplicationFiled: October 9, 2015Publication date: February 4, 2016Inventors: Mark Ferriss, Arun S. Natarajan, Benjamin D. Parker, Alexander V. Rylyakov, Jose A. Tierno, Soner Yaldiz
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Patent number: 9157950Abstract: A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.Type: GrantFiled: April 18, 2011Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Mark Ferriss, Arun S. Natarajan, Benjamin D. Parker, Alexander V. Rylyakov, Jose A. Tierno, Soner Yaldiz
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Patent number: 8629701Abstract: A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter.Type: GrantFiled: July 22, 2013Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Mark A. Ferriss, Arun Natarajan, Benjamin Parker, Alexander Rylyakov, Jose A. Tierno, Soner Yaldiz
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Publication number: 20130307588Abstract: A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter.Type: ApplicationFiled: July 22, 2013Publication date: November 21, 2013Applicant: International Business Machines CorporationInventors: Mark A. Ferriss, Arun Natarajan, Benjamin Parker, Alexander Rylyakov, Jose A. Tierno, Soner Yaldiz
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Patent number: 8493113Abstract: A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter.Type: GrantFiled: September 12, 2011Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Mark A. Ferriss, Arun Natarajan, Benjamin Parker, Alexander Rylyakov, Jose A. Tierno, Soner Yaldiz
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Publication number: 20130063192Abstract: A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark A. Ferriss, Arun Natarajan, Benjamin Parker, Alexander Rylyakov, Jose A. Tierno, Soner Yaldiz
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Publication number: 20120262149Abstract: A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.Type: ApplicationFiled: April 18, 2011Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark Ferriss, Arun S. Natarajan, Benjamin D. Parker, Alexander V. Rylyakov, Jose A. Tierno, Soner Yaldiz