Patents by Inventor Song-Fu Liao
Song-Fu Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11917831Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.Type: GrantFiled: August 5, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20240064993Abstract: A method of fabricating a transistor structure is provided. The method comprises forming a gate electrode in a dielectric layer of an interconnect structure; forming a monolayer on a portion of the dielectric layer laterally spaced from the gate electrode; sequentially forming a ferroelectric layer, a barrier layer and a channel layer on the gate electrode; and forming a source/drain electrode on the channel layer.Type: ApplicationFiled: August 11, 2022Publication date: February 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Song-Fu Liao, Kuo-Chang Chiang, Hai-Ching Chen, Chung-Te Lin
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Patent number: 11908936Abstract: A ferroelectric field effect transistor (FeFET) having a double-gate structure includes a first gate electrode, a first ferroelectric material layer over the first gate electrode, a semiconductor channel layer over the first ferroelectric material layer, source and drain electrodes contacting the semiconductor channel layer, a second ferroelectric material layer over the semiconductor channel layer, and a second gate electrode over the second ferroelectric material layer.Type: GrantFiled: September 21, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yen-Chieh Huang, Song-Fu Liao, Po-Ting Lin, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
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Publication number: 20240032300Abstract: In some embodiments, the present disclosure relates to a 3D memory device, including a plurality of gate lines interleaved between a plurality of dielectric layers in a vertical direction, the plurality of gate lines forming recesses between the plurality of dielectric layers; a source/drain line disposed next to the plurality of dielectric layers, spaced from the plurality of gate lines by the recesses in a lateral direction; a ferroelectric film arranged laterally between sidewalls of the plurality of gate lines and the source/drain line and confined within the recesses; and a semiconductor film disposed within the recesses and spacing the ferroelectric film from the source/drain line.Type: ApplicationFiled: July 19, 2022Publication date: January 25, 2024Inventors: Song-Fu Liao, Kuo-Chang Chiang, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20230411522Abstract: A ferroelectric field effect transistor (FeFET) having a double-gate structure includes a first gate electrode, a first ferroelectric material layer over the first gate electrode, a semiconductor channel layer over the first ferroelectric material layer, source and drain electrodes contacting the semiconductor channel layer, a second ferroelectric material layer over the semiconductor channel layer, and a second gate electrode over the second ferroelectric material layer.Type: ApplicationFiled: August 8, 2023Publication date: December 21, 2023Inventors: Yen-Chieh HUANG, Song-Fu LIAO, Po-Ting LIN, Hai-Ching CHEN, Sai-Hooi YEONG, Yu-Ming LIN, Chung-Te LIN
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FERROELECTRIC MEMORY DEVICES HAVING IMPROVED FERROELECTRIC PROPERTIES AND METHODS OF MAKING THE SAME
Publication number: 20230378354Abstract: Ferroelectric devices, including FeFET and/or FeRAM devices, include ferroelectric material layers deposited using atomic layer deposition (ALD). By controlling parameters of the ALD deposition sequence, the crystal structure and ferroelectric properties of the ferroelectric layer may be engineered. An ALD deposition sequence including relatively shorter precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having relatively uniform crystal grain sizes and a small mean grain size (e.g., ?3 nm), which may provide effective ferroelectric performance. An ALD deposition sequence including relatively longer precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having less uniform crystal grain sizes and a larger mean grain size (e.g., ?7 nm).Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Po-Ting LIN, Song-Fu LIAO, Rainer Yen-Chieh HUANG, Hai-Ching CHEN, Yu-Ming LIN, Chung-Te LIN -
Publication number: 20230369420Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC). The IC includes a substrate and an electrode disposed over the substrate. A ferroelectric layer is vertically stacked with the electrode. A seed layer that includes oxygen is vertically stacked between the electrode and the ferroelectric layer. The ferroelectric layer has a substantially uniform orthorhombic crystalline phase.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Yen-Chieh Huang, Po-Ting Lin, Song-Fu Liao, Hai-Ching Chen, Chung-Te Lin
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Patent number: 11817498Abstract: Ferroelectric structures, including a ferroelectric field effect transistors (FeFETs), and methods of making the same are disclosed which have improved ferroelectric properties and device performance. A FeFET device including a ferroelectric material gate dielectric layer and a metal oxide semiconductor channel layer is disclosed having improved ferroelectric characteristics, such as increased remnant polarization, low defects, and increased carrier mobility for improved device performance.Type: GrantFiled: December 7, 2022Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yen-Chieh Huang, Po-Ting Lin, Hai-Ching Chen, Song-Fu Liao, Yu-Ming Lin
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Patent number: 11810956Abstract: In some embodiments, the present disclosure relates to a method for forming an integrated circuit (IC), including forming a first electrode layer having a first metal over a substrate, performing a first atomic layer deposition (ALD) pulse that exposes the first electrode layer to oxygen atoms, exposing the first electrode layer to a first temperature, the first temperature causing the first electrode layer to react with the oxygen atoms to form a seed structure over the first electrode layer, and performing a series of ALD pulses at a second temperature to form a ferroelectric structure over the seed structure. The second temperature is less than the first temperature and the ferroelectric structure is configured to store a data state.Type: GrantFiled: January 6, 2022Date of Patent: November 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Chieh Huang, Po-Ting Lin, Song-Fu Liao, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20230262989Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a first electrode structure disposed in a substrate. A first ferroelectric structure is disposed on a first side of the first electrode structure. A channel structure is disposed on a first side of the first ferroelectric structure. The channel structure includes a plurality of individual channel structures and a plurality of insulator structures. The plurality of individual channel structures and the plurality of insulator structures are alternately stacked. A pair of source/drain (S/D) structures are disposed on the first side of the first ferroelectric structure. The pair of S/D structures extend vertically through the channel structure, and the first electrode structure is disposed laterally between the S/D structures of the pair of S/D structures.Type: ApplicationFiled: February 16, 2022Publication date: August 17, 2023Inventors: Yen-Chieh Huang, Po-Ting Lin, Song-Fu Liao, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
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Publication number: 20230253463Abstract: A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multipleType: ApplicationFiled: April 14, 2023Publication date: August 10, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Song-Fu LIAO, Hai-Ching CHEN, Chung-Te LIN
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Publication number: 20230247841Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.Type: ApplicationFiled: February 2, 2022Publication date: August 3, 2023Inventors: Yen-Chieh Huang, Po-Ting Lin, Song-Fu Liao, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
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Patent number: 11690228Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.Type: GrantFiled: February 25, 2021Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20230170418Abstract: Ferroelectric structures, including a ferroelectric field effect transistors (FeFETs), and methods of making the same are disclosed which have improved ferroelectric properties and device performance. A FeFET device including a ferroelectric material gate dielectric layer and a metal oxide semiconductor channel layer is disclosed having improved ferroelectric characteristics, such as increased remnant polarization, low defects, and increased carrier mobility for improved device performance.Type: ApplicationFiled: December 7, 2022Publication date: June 1, 2023Inventors: Yen-Chieh HUANG, Po-Ting LIN, Hai-Ching CHEN, Song-Fu LIAO, Yu-Ming LIN
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Patent number: 11652148Abstract: A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multipleType: GrantFiled: September 10, 2021Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Song-Fu Liao, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20230143625Abstract: In some embodiments, the present disclosure relates to a method for forming an integrated circuit (IC), including forming a first electrode layer having a first metal over a substrate, performing a first atomic layer deposition (ALD) pulse that exposes the first electrode layer to oxygen atoms, exposing the first electrode layer to a first temperature, the first temperature causing the first electrode layer to react with the oxygen atoms to form a seed structure over the first electrode layer, and performing a series of ALD pulses at a second temperature to form a ferroelectric structure over the seed structure. The second temperature is less than the first temperature and the ferroelectric structure is configured to store a data state.Type: ApplicationFiled: January 6, 2022Publication date: May 11, 2023Inventors: Yen-Chieh Huang, Po-Ting Lin, Song-Fu Liao, Hai-Ching Chen, Chung-Te Lin
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Patent number: 11527649Abstract: Ferroelectric structures, including a ferroelectric field effect transistors (FeFETs), and methods of making the same are disclosed which have improved ferroelectric properties and device performance. A FeFET device including a ferroelectric material gate dielectric layer and a metal oxide semiconductor channel layer is disclosed having improved ferroelectric characteristics, such as increased remnant polarization, low defects, and increased carrier mobility for improved device performance.Type: GrantFiled: August 30, 2021Date of Patent: December 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yen-Chieh Huang, Po-Ting Lin, Hai-Ching Chen, Song-Fu Liao, Yu-Ming Lin, Chung-Te Lin
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Publication number: 20220384460Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.Type: ApplicationFiled: August 5, 2022Publication date: December 1, 2022Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20220367648Abstract: A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multipleType: ApplicationFiled: September 10, 2021Publication date: November 17, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Song-Fu LIAO, Hai-Ching CHEN, Chung-Te LIN
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FERROELECTRIC MEMORY DEVICES HAVING IMPROVED FERROELECTRIC PROPERTIES AND METHODS OF MAKING THE SAME
Publication number: 20220352379Abstract: Ferroelectric devices, including FeFET and/or FeRAM devices, include ferroelectric material layers deposited using atomic layer deposition (ALD). By controlling parameters of the ALD deposition sequence, the crystal structure and ferroelectric properties of the ferroelectric layer may be engineered. An ALD deposition sequence including relatively shorter precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having relatively uniform crystal grain sizes and a small mean grain size (e.g., ?3 nm), which may provide effective ferroelectric performance. An ALD deposition sequence including relatively longer precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having less uniform crystal grain sizes and a larger mean grain size (e.g., ?7 nm).Type: ApplicationFiled: September 22, 2021Publication date: November 3, 2022Inventors: Po-Ting LIN, Song-Fu LIAO, Rainer, Yen-Chieh HUANG, Hai-Ching CHEN, Yu-Ming LIN, Chung-Te LIN