Abstract: A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.

Abstract: A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device includes forming a first gate insulating film on a substrate for a first device, forming a first gate electrode on the first gate insulating film; forming a mask pattern on the first gate electrode to expose opposing end portions of the first gate electrode, wherein a length of the mask pattern is smaller than a length of the first gate electrode; performing ion implantation through the exposed opposing end portions of the first gate electrode using the mask pattern to simultaneously form first and second drift regions in the substrate; forming spacers on sidewalls of the first gate electrode, respectively; and forming a first source region and a first drain region in the first and second drift regions, respectively.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device includes forming a first gate insulating film on a substrate for a first device, forming a first gate electrode on the first gate insulating film; forming a mask pattern on the first gate electrode to expose opposing end portions of the first gate electrode, wherein a length of the mask pattern is smaller than a length of the first gate electrode; performing ion implantation through the exposed opposing end portions of the first gate electrode using the mask pattern to simultaneously form first and second drift regions in the substrate; forming spacers on sidewalls of the first gate electrode, respectively; and forming a first source region and a first drain region in the first and second drift regions, respectively.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device includes forming a first gate insulating film on a substrate for a first device, forming a first gate electrode on the first gate insulating film; forming a mask pattern on the first gate electrode to expose opposing end portions of the first gate electrode, wherein a length of the mask pattern is smaller than a length of the first gate electrode; performing ion implantation through the exposed opposing end portions of the first gate electrode using the mask pattern to simultaneously form first and second drift regions in the substrate; forming spacers on sidewalls of the first gate electrode, respectively; and forming a first source region and a first drain region in the first and second drift regions, respectively.

Abstract: The present invention relates to a memory device including a substrate and a lower electrode, buffer layer, seed layer, Magnetic Tunnel Junction (MTJ), capping layer, synthetic antiferromagnetic layer, and upper electrode formed on the substrate.

Abstract: The present invention relates to a memory device including a substrate and a lower electrode, buffer layer, seed layer, Magnetic Tunnel Junction (MTJ), capping layer, synthetic exchange diamagnetic layer, and upper electrode formed on the substrate.