Patents by Inventor Song Hyeuk Im
Song Hyeuk Im has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9570391Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. When forming a bit line of a cell region, a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of overall bit line is reduced, resulting in reduction in parasitic capacitance.Type: GrantFiled: April 10, 2015Date of Patent: February 14, 2017Assignee: SK HYNIX INC.Inventor: Song Hyeuk Im
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Publication number: 20150214147Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. When forming a bit line of a cell region, a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of overall bit line is reduced, resulting in reduction in parasitic capacitance.Type: ApplicationFiled: April 10, 2015Publication date: July 30, 2015Inventor: Song Hyeuk IM
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Patent number: 8674473Abstract: A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.Type: GrantFiled: August 16, 2011Date of Patent: March 18, 2014Assignee: Hynix Semiconductor Inc.Inventor: Song Hyeuk Im
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Publication number: 20130256904Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. When forming a bit line of a cell region, a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of overall bit line is reduced, resulting in reduction in parasitic capacitance.Type: ApplicationFiled: September 7, 2012Publication date: October 3, 2013Applicant: SK Hynix Inc.Inventor: Song Hyeuk IM
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Patent number: 8338246Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming a device isolation film and prevents the punch-through phenomenon to improve electrical characteristics of semiconductor devices and increase product yield.Type: GrantFiled: September 30, 2009Date of Patent: December 25, 2012Assignee: Hynix Semiconductor Inc.Inventor: Song Hyeuk Im
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Publication number: 20120273919Abstract: A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.Type: ApplicationFiled: August 16, 2011Publication date: November 1, 2012Applicant: Hynix Semiconductor Inc.Inventor: Song Hyeuk IM
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Patent number: 8164140Abstract: A method for manufacturing a semiconductor device comprises forming a first spacer layer at sidewalls of one or more gate electrodes, forming a trench by etching an isolation insulating layer exposed between the gate electrodes, forming a second spacer layer on sidewalls of the gate electrodes and an inner surface of the trench and forming an interlayer insulating layer between the gate electrodes.Type: GrantFiled: May 26, 2011Date of Patent: April 24, 2012Assignee: Hynix Semiconductor Inc.Inventor: Song hyeuk Im
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Publication number: 20110220993Abstract: A method for manufacturing a semiconductor device comprises forming a first spacer layer at sidewalls of one or more gate electrodes, forming a trench by etching an isolation insulating layer exposed between the gate electrodes, forming a second spacer layer on sidewalls of the gate electrodes and an inner surface of the trench and forming an interlayer insulating layer between the gate electrodes.Type: ApplicationFiled: May 26, 2011Publication date: September 15, 2011Applicant: Hynix Semiconductor Inc.Inventor: Song Hyeuk IM
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Patent number: 8012833Abstract: A method for fabricating a semiconductor device includes forming an insulating pattern over a semiconductor substrate. An epitaxial growth layer is formed over the semiconductor substrate exposed by the insulating pattern to fill the insulating pattern with the epitaxial growth layer. A recess gate having a recess channel is formed. The recess channel is disposed between two neighboring insulating patterns.Type: GrantFiled: December 28, 2007Date of Patent: September 6, 2011Assignee: Hynix Semiconductor Inc.Inventor: Song Hyeuk Im
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Patent number: 7977188Abstract: A method for manufacturing a semiconductor device comprises forming a first spacer layer at sidewalls of one or more gate electrodes, forming a trench by etching an isolation insulating layer exposed between the gate electrodes, forming a second spacer layer on sidewalls of the gate electrodes and an inner surface of the trench and forming an interlayer insulating layer between the gate electrodes.Type: GrantFiled: June 26, 2009Date of Patent: July 12, 2011Assignee: Hynix Semiconductor Inc.Inventor: Song hyeuk Im
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Publication number: 20100155832Abstract: A method for manufacturing a semiconductor device comprises forming a first spacer layer at sidewalls of one or more gate electrodes, forming a trench by etching an isolation insulating layer exposed between the gate electrodes, forming a second spacer layer on sidewalls of the gate electrodes and an inner surface of the trench and forming an interlayer insulating layer between the gate electrodes.Type: ApplicationFiled: June 26, 2009Publication date: June 24, 2010Applicant: Hynix Semiconductor Inc.Inventor: Song Hyeuk IM
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Publication number: 20100019315Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming a device isolation film and prevents the punch-through phenomenon to improve electrical characteristics of semiconductor devices and increase product yield.Type: ApplicationFiled: September 30, 2009Publication date: January 28, 2010Applicant: Hynix Semiconductor Inc.Inventor: Song Hyeuk IM
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Patent number: 7601582Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming a device isolation film and prevents the punch-through phenomenon to improve electrical characteristics of semiconductor devices and increase product yield.Type: GrantFiled: September 29, 2006Date of Patent: October 13, 2009Assignee: Hynix Semiconductor Inc.Inventor: Song Hyeuk Im
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Publication number: 20090072344Abstract: A method for fabricating a semiconductor device includes forming an insulating pattern over a semiconductor substrate. An epitaxial growth layer is formed over the semiconductor substrate exposed by the insulating pattern to fill the insulating pattern with the epitaxial growth layer. A recess gate having a recess channel is formed. The recess channel is disposed between two neighboring insulating patterns.Type: ApplicationFiled: December 28, 2007Publication date: March 19, 2009Applicant: Hynix Semiconductor, Inc.Inventor: Song Hyeuk Im
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Patent number: 7358144Abstract: A method for fabricating a semiconductor device includes forming first, second, and third device structures in a semiconductor substrate. Each device structure includes a first film, a second film over the first film, and a third film over the second film. The first and third device structures are device isolation structures. A portion of the second device structure is etched to define a bit line contact region, the bit line contact region extending from an upper surface of the second device structure to a lower surface of the second device structure. The second film of the second device structure is etched to define an under-cut space between the first and second films. A semiconductor layer is formed within the under-cut space and the bit line contact region. The third film of the second device structure is etched or removed to define a recess, the recess defining a gate region. A gate structure is formed at least partly within the recess.Type: GrantFiled: April 10, 2006Date of Patent: April 15, 2008Assignee: Hynix Semiconductor Inc.Inventor: Song Hyeuk Im
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Publication number: 20070264789Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming a device isolation film and prevents the punch-through phenomenon to improve electrical characteristics of semiconductor devices and increase product yield.Type: ApplicationFiled: September 29, 2006Publication date: November 15, 2007Applicant: Hynix Semiconductor Inc.Inventor: Song Hyeuk Im
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Publication number: 20070173015Abstract: A method for fabricating a semiconductor device includes forming first, second, and third device structures in a semiconductor substrate. Each device structure includes a first film, a second film over the first film, and a third film over the second film. The first and third device structures are device isolation structures. A portion of the second device structure is etched to define a bit line contact region, the bit line contact region extending from an upper surface of the second device structure to a lower surface of the second device structure. The second film of the second device structure is etched to define an under-cut space between the first and second films. A semiconductor layer is formed within the under-cut space and the bit line contact region. The third film of the second device structure is etched or removed to define a recess, the recess defining a gate region. A gate structure is formed at least partly within the recess.Type: ApplicationFiled: April 10, 2006Publication date: July 26, 2007Applicant: Hynix Semiconductor Inc.Inventor: Song Hyeuk Im