Patents by Inventor Song NA

Song NA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155829
    Abstract: A semiconductor memory device may include a plurality of bit lines extending in a first direction on a substrate, a plurality of active pillars respectively on the bit lines, a word line extending in a second direction along the plurality of active pillars, a plurality of landing pads respectively on the plurality of active pillars, and a plurality of data storage patterns respectively on the plurality of landing pads. Each of the plurality of active pillars may have a length extending in a direction perpendicular to an upper surface of the substrate. The word line has a wavy shape when viewed in a plan view.
    Type: Application
    Filed: June 22, 2023
    Publication date: May 9, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Changsik KIM, Jae Won NA, Junhwa SONG, Dong-Sik PARK
  • Patent number: 11924473
    Abstract: Disclosed herein is a method for decoding a video including determining a coding unit to be decoded by block partitioning, decoding prediction syntaxes for the coding unit, the prediction syntaxes including a skip flag indicating whether the coding unit is encoded in a skip mode, after the decoding of the prediction syntaxes, decoding transform syntaxes including a transformation/quantization skip flag and a coding unit cbf, wherein the transformation/quantization skip flag indicates whether inverse transformation, inverse quantization, and at least part of in-loop filterings are skipped, and the coding unit cbf indicates whether all coefficients in a luma block and two chroma blocks constituting the coding unit are zero, and reconstructing the coding unit based on the prediction syntaxes and the transform syntaxes.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: March 5, 2024
    Assignee: SK TELECOM CO., LTD.
    Inventors: Sun Young Lee, Jeong-yeon Lim, Tae Young Na, Gyeong-taek Lee, Jae-seob Shin, Se Hoon Son, Hyo Song Kim
  • Patent number: 11501981
    Abstract: Disclosed is a method for fabricating a semiconductor package. A mold press with upper and lower chases is used. A molded underfill (MUF) material is dispensed on a bottom surface of a mold cavity to form a first dispensed pattern with a serpentine shape. A base substrate on which die stacks are mounted is loaded on the upper chase. The mold cavity in which the die stacks are inserted is closed and MUF material flows between the die stacks to impregnate the die stacks.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Kyung Beom Seo, Jong Kyu Moon, Jong Hyock Park, Song Na
  • Publication number: 20220115247
    Abstract: Disclosed is a method for fabricating a semiconductor package. A mold press with upper and lower chases is used. A molded underfill (MUF) material is dispensed on a bottom surface of a mold cavity to form a first dispensed pattern with a serpentine shape. A base substrate on which die stacks are mounted is loaded on the upper chase. The mold cavity in which the die stacks are inserted is closed and MUF material flows between the die stacks to impregnate the die stacks.
    Type: Application
    Filed: March 16, 2021
    Publication date: April 14, 2022
    Applicant: SK hynix Inc.
    Inventors: Kyung Beom SEO, Jong Kyu MOON, Jong Hyock PARK, Song NA
  • Patent number: 9257413
    Abstract: Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: February 9, 2016
    Assignee: SK HYNIX INC.
    Inventors: Seung Taek Yang, Jong Hoon Kim, Tac Keun Oh, Song Na
  • Publication number: 20150061120
    Abstract: Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.
    Type: Application
    Filed: February 25, 2014
    Publication date: March 5, 2015
    Applicant: SK hynix Inc.
    Inventors: Seung Taek YANG, Jong Hoon KIM, Tac Keun OH, Song NA