Abstract: A power switching circuit receives a first power, a second power and a switching signal, and generates an output power. The power switching circuit includes a first power path and a second power path. The first power path is connected with the first power. The second power path is connected with the second power. When the switching signal in a logic high level, the first power path is in a conducting state and the second power path is in a non-conducting state. Consequently, the first power is selected as the output power by the power switching circuit. When the switching signal in a logic low level, the first power path is in the non-conducting state and the second power path is in the conducting state. Consequently, the second power is selected as the output power by the power switching circuit.

Abstract: A power switching circuit receives a first power, a second power and a switching signal, and generates an output power. The power switching circuit includes a first power path and a second power path. The first power path is connected with the first power. The second power path is connected with the second power. When the switching signal in a logic high level, the first power path is in a conducting state and the second power path is in a non-conducting state. Consequently, the first power is selected as the output power by the power switching circuit. When the switching signal in a logic low level, the first power path is in the non-conducting state and the second power path is in the conducting state. Consequently, the second power is selected as the output power by the power switching circuit.

Abstract: A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

Abstract: A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

Abstract: A triangular wave generator, comprising: a first frequency divider, for utilizing a first positive integer to divide a first frequency of a first periodical signal to generate a first frequency-divided signal; a second frequency divider, for utilizing a second positive integer to divide a second frequency, which equals the first frequency multiplying a third positive integer, of a second periodical signal to generate a second frequency-divided signal; and an up/down counter, for generating a triangular wave first and second frequency-divided frequencies respectively belonging to first and second frequency divided signals; wherein a frequency of the triangular wave equals to the first frequency-divided frequency, and an amplitude of the triangular wave is determined according to a ratio of the first and second frequency-divided frequencies.

Abstract: A timing-signal generator includes a PLL circuit, one or more rising/falling edge generating unit and one or more timing-signal generating unit. In response to a reference signal with a frequency Fref, the PLL outputs M voltage controlled signals with the same frequency Fvco=N*Fref and equally distributed phase differences. The rising/falling edge generating unit is for generating a rising point signal and a falling point signal corresponding to respective ones one of M*P candidate timing points which are defined in a cycle of the reference signal according to the M voltage controlled signals. The timing-signal generating unit coupled to the rising/falling edge generating unit is for generating a timing signal which toggles high in response to the rising point signal and toggles low in response to the falling point signal.

Abstract: A time constant calibration device includes: a first voltage generating circuit utilizing a first current passing through a capacitive component to generate a first voltage; a second voltage generating circuit utilizing a second current passing through a resistive component to generate a second voltage; and a comparing circuit for comparing the first voltage with the second voltage to generate a comparing signal, wherein the first voltage generating circuit comprises an analog adjusting component for adjusting the first voltage according to the comparing signal until the first voltage is equal to the second voltage, whereby an RC time constant defined by an equivalent capacitance corresponding to the first current passing through the capacitive component and an equivalent impedance corresponding to the second current passing through the resistive component reaches a predetermined value.

Abstract: A spread-spectrum clock generator (SSCG) and a spread-spectrum clock generating method are provided. The SSCG includes a first spread-spectrum module, a second spread-spectrum module, and a waveform module. The first spread-spectrum module generates a first spread-spectrum clock signal by modulating the frequency of a first input clock signal with a parallel delay configuration. The second spread-spectrum module generates a second spread-spectrum clock signal by modulating the frequency of a second input clock signal with the same parallel delay configuration. The waveform module is coupled to the first spread-spectrum module and the second spread-spectrum module for generating an output spread-spectrum clock signal according to the first and the second spread-spectrum clock signals.

Abstract: A spread-spectrum clock generator is provided, which includes a modulation module and a voltage-controlled delay line (VCDL). The modulation module provides a control voltage. The VCDL is coupled to the modulation module and is configured for modulating the frequency of an input clock signal according to the control voltage, so as to output an output clock signal. The modulation profile of the output clock signal is a periodic function of time.

Abstract: A timing-signal generator includes a PLL circuit, one or more rising/falling edge generating unit and one or more timing-signal generating unit. In response to a reference signal with a frequency Fref, the PLL outputs M voltage controlled signals with the same frequency Fvco=N*Fref and equally distributed phase differences. The rising/falling edge generating unit is for generating a rising point signal and a falling point signal corresponding to respective ones one of M*P candidate timing points which are defined in a cycle of the reference signal according to the M voltage controlled signals. The timing-signal generating unit coupled to the rising/falling edge generating unit is for generating a timing signal which toggles high in response to the rising point signal and toggles low in response to the falling point signal.

Abstract: A time constant calibration device includes: a first voltage generating circuit utilizing a first current passing through a capacitive component to generate a first voltage; a second voltage generating circuit utilizing a second current passing through a resistive component to generate a second voltage; and a comparing circuit for comparing the first voltage with the second voltage to generate a comparing signal, wherein the first voltage generating circuit comprises an analog adjusting component for adjusting the first voltage according to the comparing signal until the first voltage is equal to the second voltage whereby an RC time constant defined by an equivalent capacitance corresponding to the first current passing through the capacitive component and an equivalent impedance corresponding to the second current passing through the resistive component reaches a predetermined value.

Abstract: An automatic switching phase-locked loop (PLL) is disclosed, including a phase detector, a charge pump generating a pump current, a band selector receiving a control voltage to produce a band selection signal and a voltage setting signal based the control voltage, a loop filter generating the control voltage corresponding to the pump current and setting the control voltage based on the voltage setting signal, and a multi-band voltage control oscillator (VCO) coupled to the control voltage and the band selection signal, selecting one of a plurality of operating bands based on the band selection signal, and providing an output signal of a frequency within the selected operating band based on the control voltage.

Abstract: An automatic switching phase-locked loop (PLL) is disclosed, including a phase detector, a charge pump generating a pump current, a band selector receiving a control voltage to produce a band selection signal and a voltage setting signal based the control voltage, a loop filter generating the control voltage corresponding to the pump current and setting the control voltage based on the voltage setting signal, and a multi-band voltage control oscillator (VCO) coupled to the control voltage and the band selection signal, selecting one of a plurality of operating bands based on the band selection signal, and providing an output signal of a frequency within the selected operating band based on the control voltage.

Abstract: A frequency comparator comparing frequencies of a first clock signal and a reference clock signal. The frequency comparator includes a phase-frequency detector and a comparison module. The phase-frequency detector receives the first clock signal and the reference clock signal, and outputs an up clock signal and a down clock signal. The pulse-width difference between the up clock signal and the down clock signal corresponds to the phase difference between the first clock signal and the reference clock signal. The comparison module compares the frequencies of the first clock signal and the reference clock signal based on how many times the pulse width of the up clock signal is larger or shorter than that of the down clock signal in a predetermined period.

Abstract: A frequency comparator is disclosed, comparing frequencies of a first clock signal and a reference clock signal, comprising a phase-frequency detector and a comparison module. The phase-frequency detector receives the first clock signal and the reference clock signal, outputting an up clock signal and a down clock signal, wherein the pulse-width difference between the up clock signal and the down clock signal corresponds to the phase difference between the first clock signal and the reference clock signal. The comparison module compares the frequencies of the first clock signal and the reference clock signal based on how many times the pulse width of the up clock signal is larger or shorter than that of the down clock signal in a predetermined period.

Abstract: The present invention discloses a delay-locked loop device capable of anti-false-locking, which comprises: a voltage control delay circuit comprising a plurality of delay units in a series for generating a delayed phase according to a reference phase and a control voltage; a phase detector coupled to the voltage control delay circuit for generating a control signal according to a lock indication signal, the reference phase, and the delayed phase; a charge pump coupled to the phase detector for transmitting the control voltage to the voltage control delay circuit according to the control signal; and a lock detector coupled to the voltage control delay circuit for generating the lock indication signal for the phase detector according to output phases of at least one delay unit of the voltage control delay circuit.

Abstract: The present invention discloses a delay-locked loop device capable of anti-false-locking, which comprises: a voltage control delay circuit comprising a plurality of delay units in a series for generating a delayed phase according to a reference phase and a control voltage; a phase detector coupled to the voltage control delay circuit for generating a control signal according to a lock indication signal, the reference phase, and the delayed phase; a charge pump coupled to the phase detector for transmitting the control voltage to the voltage control delay circuit according to the control signal; and a lock detector coupled to the voltage control delay circuit for generating the lock indication signal for the phase detector according to output phases of at least one delay unit of the voltage control delay circuit.