Abstract: Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state. Then the method includes applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value. This step is repeated until the high resistance state resistance value is greater than the lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value. The reverse resetting voltage pulse has a second polarity being opposite the first polarity. This step is repeated until all the high resistance state resistance value is less than the upper resistance limit value.

Abstract: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.

Abstract: A free ferromagnetic data storage layer of an MRAM cell is coupled to a free ferromagnetic stabilization layer, which stabilization layer is directly electrically coupled to a contact electrode, on one side, and is separated from the free ferromagnetic data storage layer, on an opposite side, by a spacer layer. The spacer layer provides for the coupling between the two free layers, which coupling is one of: a ferromagnetic coupling and an antiferromagnetic coupling.

Abstract: A non-volatile memory cell that has a charge source region, a charge storage region, and a crested tunnel barrier layer that has a potential energy profile which peaks between the charge source region and the charge storage region. The tunnel barrier layer has multiple high-K dielectric materials, either as individual layers or as compositionally graded materials.

Abstract: A multilayered magnetoresistive device includes a specular layer positioned on at least one sidewall and a copper layer is positioned between the specular layer and the sidewall.

Abstract: The present invention relates to a memory cell including a first reference layer having a first magnetization with a first magnetization direction and a second reference layer having a second magnetization with a second magnetization direction substantially perpendicular to the first magnetization direction. A storage layer is disposed between the first reference layer and second reference layer and has a third magnetization direction about 45° from the first magnetization direction and about 135° from the second magnetization direction when the memory cell is in a first data state, and a fourth magnetization direction opposite the third magnetization direction when the memory cell is in a second data state.

Abstract: Spin torque magnetic logic devices that function as memory devices and that can be reconfigured or reprogrammed as desired. In some embodiments, the logic device is a single magnetic element, having a pinned layer, a free layer, and a barrier layer therebetween, or in other embodiments, the logic device has two magnetic elements in series. Two input currents can be applied through the element to configure or program the element. In use, logic input data, such as current, is passed through the programmed element, defining the resistance across the element and the resulting logic output. The magnetic logic device can be used for an all-function-in-one magnetic chip.

Abstract: Spin torque magnetic logic device having at least one input element and an output element. Current is applied through the input element(s), and the resulting resistance or voltage across the output element is measured. The input element(s) include a free layer and the output element includes a free layer that is electrically connected to the free layer of the input element. The free layers of the input element and the output element may be electrically connected via magnetostatic coupling, or may be physically coupled. In some embodiments, the output element may have more than one free layer.

Abstract: A conductive write line of a memory device includes a resistive heating portion for setting and resetting a phase-change material (PCM) storage cell of the device. A dielectric interface extends between the resistive heating portion of the write line and a side of the storage cell, and provides electrical insulation while allowing for thermal coupling between the resistive heating portion and the storage cell. A width of the resistive heating portion of the write line may be less than a width of the storage cell and/or may be less than a width of adjacent portions of the write line, between which the resistive heating portion extends. The side of the storage cell may define a channel of the storage cell through which the write line passes, such that the resistive heating portion is located within the channel.

Abstract: A micro-electromechanical systems (MEMS) disc drive includes high-precision and integrated components to allow for increased functionality, robustness and reduced size as compared to currently produced disc drives. Integrating multiple subcomponents of the disc drive using batch processing provides low manufacturing costs. Furthermore, using MEMS techniques, new features can be added to disc drives. For example, an environmental control component, an accelerometer and/or a thermometer may be integrated into the housing of the disc drive.

Abstract: In general, the invention is directed to techniques for integrated interconnects with a set of disc drives. The interconnects allow for a set of disc drives to be positioned in an array; for example, as set of disc drives may be stacked to communicate with a device through a single interface of the device. The interconnects may be formed as vias within the housing of the disc drives. Vias may produced using MEMS techniques, e.g., electroplating, as part of the manufacturing processes of the disc drive itself.

Abstract: Random access memory cells having a short phase change bridge structure and methods of making the bridge structure via shadow deposition. The short bridge structure reduces the heating efficiency needed to switch the logic state of the memory cell. In one particular embodiment, the memory cell has a first electrode and a second electrode with a gap therebetween. The first electrode has an end at least partially non-orthogonal to the substrate and the second electrode has an end at least partially non-orthogonal to the substrate. A phase change material bridge extends over at least a portion of the first electrode, over at least a portion of the second electrode, and within the gap. An insulative material encompasses at least a portion of the phase change material bridge.

Abstract: Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state and setting a counter to zero. Then the method includes applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value and adding one to the counter. This step is repeated until either the counter reaches a predetermined number or until the high resistance state resistance value is greater than the lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value and adding one to the counter.

Abstract: A shock sensor comprises a substrate and at least one flexure coupled to the substrate and configured to deflect upon an application of force to the shock sensor sufficient to deflect the flexure. Deflection of the at least one flexure produces a detectable change in an electrical property of the shock sensor. Examples of detectable changes in an electrical property of the shock sensor include an open circuit condition, a closed circuit condition, and a variation in voltage of a piezo-electric detector. In some embodiments, the change in the electrical property of the shock sensor may be remotely read by interrogation of a radio frequency identification transponder positioned on the substrate using a remote radio frequency identification transceiver. The disclosure also relates to a shock sensing system and method of shock detection.

Abstract: Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme.

Abstract: Method and apparatus for constructing a non-volatile memory cell, such as a modified RRAM cell. In some embodiments, a memory cell comprises a resistive storage layer disposed between a first electrode layer and a second electrode layer. Further in some embodiments, the storage layer has a localized region of decreased thickness to facilitate formation of a conductive filament through the storage layer from the first electrode to the second electrode.

Abstract: Apparatus to generate signals with multiple phases are described. The apparatus includes a fixed multilayer stack providing a varying magnetic field and at least two sensors adjacent the fixed multilayer stack to sense the varying magnetic field and generate at least two output signals. The frequency of the output signals can be tuned by an input current.

Abstract: Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at least two states and is proximate the source region. A second solid electrolyte cell is over the insulating layer and has a capacitance or resistance that is controllable between at least two states and is proximate the drain region. An insulating element isolates the first solid electrolyte cell from the second solid electrolyte cell. A first anode is electrically coupled to the first solid electrolyte cell. The first solid electrolyte cell is between the anode and the insulating layer. A second anode is electrically coupled to the second solid electrolyte cell. The second solid electrolyte cell is between the anode and the insulating layer.

Abstract: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

Abstract: Methods for making a programmable metallization memory cell are disclosed.