Abstract: A bidirectional shifter circuit is disclosed for shifting an inputted data word a chosen number of bit positions in either a first or a second chosen direction. The bidirectional shifter circuit is provided with a first bit-reversing circuit which receives an inputted data word. In response to choosing a first shift direction, the first bit-reversing circuit outputs the data word with the bits in their original order. In response to choosing the second shift direction, the first bit-reversing circuit outputs the data word with the bits in reverse order. A single-direction shifter circuit is provided which receives the data word outputted by the first bit-reversing circuit and shifts the received data word the chosen number of bit positions in the first direction.

Abstract: An IC chip operation inhibitor to prevent operation of an IC chip in a system having a clock rate that exceeds a predetermined reference clock rate for the chip. The inhibitor has a frequency detecting device that generates at least one reference frequency. It compares the system clock with the reference frequency and prevents the chip from operating if the system clock frequency is greater than the reference frequency. The invention includes an external actuating device coupled to the frequency detecting device for generating a compare enable signal to actuate the comparing function of the frequency detecting device, and for generating a frequency select signal for selecting one of the built-in reference frequencies to be compared with the system oscillating frequency. The external actuating device may be turned off in order not to actuate the comparing function of the frequency detecting device when it is sure that the system oscillating frequency will not be higher than the reference frequency.

Abstract: The present invention comprises a decoding system for decoding a data accessing instruction for accessing data stored in a plurality of registers wherein the registers are of different types including a global type, a local type, an input type and an output type, the registers being cataloged into a plurality of windows arranged in a predefined window sequence wherein each window including a plurality of registers of each of the types arranged in a predefined register sequence wherein the output registers of one of the windows being overlapping with the input registers of an adjacent window which being next in sequence of the window sequence. The decoding system comprises an instruction issuing means for issuing a data accessing instruction including a plurality of bits wherein the bits being encoded in an order corresponding to the window sequence and the register sequence and a set of bits of the instruction is used for defining a corresponding window and a corresponding type of the registers.