Patents by Inventor Song-Yu Yang

Song-Yu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240171162
    Abstract: A phase error compensation circuit and a method for compensating a phase error between a reference clock and a feedback clock are provided. The phase error compensation circuit includes a first programmable delay circuit, a second programmable delay circuit and at least one swapping circuit. The first programmable delay circuit provides a first delay. The second programmable delay circuit provides a second delay. At a present cycle, the first delay is unchanged, wherein the swapping circuit applies the first delay to the feedback clock for generating a compensated feedback clock and applies the second delay to the reference clock for generating a compensated reference clock. At a next cycle, the second delay is unchanged, where the swapping circuit applies the second delay to the feedback clock for generating the compensated feedback clock and applies the first delay to the reference clock for generating the compensated reference clock.
    Type: Application
    Filed: August 15, 2023
    Publication date: May 23, 2024
    Applicant: MEDIATEK INC.
    Inventors: Wei-Hao Chiu, Song-Yu Yang, Ang-Sheng Lin
  • Patent number: 11837995
    Abstract: A one-coil multi-core inductor-capacitor (LC) oscillator is provided. The one-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer wire and a central wire, wherein the outer wire is coupled to a first core circuit and a second core circuit, and the central wire is coupled between a first node and a second node of the outer wire. More particularly, an outer loop formed by the outer wire corresponds to a first mode of the one-coil multi-core LC oscillator, and inner loops formed by the outer wire and the central wire correspond to a second mode of the one-coil multi-core LC oscillator, where the at least one mode suppression device is configured to suppress one of the first mode and the second mode.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: December 5, 2023
    Assignee: MEDIATEK INC.
    Inventors: Hao-Wei Huang, Song-Yu Yang, Ang-Sheng Lin, Yi-Chien Tsai
  • Publication number: 20220385233
    Abstract: A one-coil multi-core inductor-capacitor (LC) oscillator is provided. The one-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer wire and a central wire, wherein the outer wire is coupled to a first core circuit and a second core circuit, and the central wire is coupled between a first node and a second node of the outer wire. More particularly, an outer loop formed by the outer wire corresponds to a first mode of the one-coil multi-core LC oscillator, and inner loops formed by the outer wire and the central wire correspond to a second mode of the one-coil multi-core LC oscillator, where the at least one mode suppression device is configured to suppress one of the first mode and the second mode.
    Type: Application
    Filed: April 27, 2022
    Publication date: December 1, 2022
    Applicant: MEDIATEK INC.
    Inventors: Hao-Wei Huang, Song-Yu Yang, Ang-Sheng Lin, Yi-Chien Tsai
  • Patent number: 11340641
    Abstract: A voltage regulator provides a load device with a regulated voltage, and includes a first regulator circuit, a second regulator circuit, a first control loop circuit, and a second control loop circuit. The load device and the first regulator circuit are connected in series. The load device and the second regulator circuit are connected in parallel. The first control loop circuit adaptively adjusts a first bias voltage of the first regulator circuit in response to a load condition at the output node of the voltage regulator, wherein the first control loop circuit includes a capacitor coupled between the first power rail and an output node of a feedback amplifier. The second control loop circuit adaptively adjusts a second bias voltage of the second regulator circuit in response to the load condition at the output node of the voltage regulator.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 24, 2022
    Assignee: MediaTek Inc.
    Inventors: Chun-Wei Chang, Song-Yu Yang, Ang-Sheng Lin
  • Publication number: 20200142436
    Abstract: A voltage regulator provides a load device with a regulated voltage, and includes a first regulator circuit, a second regulator circuit, a first control loop circuit, and a second control loop circuit. The load device and the first regulator circuit are connected in series. The load device and the second regulator circuit are connected in parallel. The first control loop circuit adaptively adjusts a first bias voltage of the first regulator circuit in response to a load condition at the output node of the voltage regulator, wherein the first control loop circuit includes a capacitor coupled between the first power rail and an output node of a feedback amplifier. The second control loop circuit adaptively adjusts a second bias voltage of the second regulator circuit in response to the load condition at the output node of the voltage regulator.
    Type: Application
    Filed: October 2, 2019
    Publication date: May 7, 2020
    Inventors: Chun-Wei Chang, Song-Yu Yang, Ang-Sheng Lin
  • Patent number: 10291237
    Abstract: An oscillator circuit has a reconfigurable oscillator amplifier. The reconfigurable oscillator amplifier is used to be coupled to a resonant circuit in parallel. The reconfigurable oscillator amplifier supports different circuit configurations for different operation modes, respectively. The reconfigurable oscillator amplifier has at least one circuit component shared by the different circuit configurations. The reconfigurable oscillator amplifier employs one of the different circuit configurations under one of the different operation modes.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: May 14, 2019
    Assignee: MEDIATEK INC.
    Inventors: Hao-Wei Huang, Yen-Tso Chen, Song-Yu Yang
  • Publication number: 20170294915
    Abstract: An oscillator circuit has a reconfigurable oscillator amplifier. The reconfigurable oscillator amplifier is used to be coupled to a resonant circuit in parallel. The reconfigurable oscillator amplifier supports different circuit configurations for different operation modes, respectively. The reconfigurable oscillator amplifier has at least one circuit component shared by the different circuit configurations. The reconfigurable oscillator amplifier employs one of the different circuit configurations under one of the different operation modes.
    Type: Application
    Filed: November 18, 2016
    Publication date: October 12, 2017
    Inventors: Hao-Wei Huang, Yen-Tso Chen, Song-Yu Yang
  • Patent number: 8664996
    Abstract: A clock generator utilized for providing a clock signal includes: a first oscillator and a switching circuit. The switching circuit is coupled to the first oscillator and a second oscillator, and utilized for receiving a first oscillating signal generated from the first oscillator and a second oscillating signal generated from the second oscillator, and selecting one of the first oscillating signal and the second oscillating signal as the clock signal according to a status signal.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: March 4, 2014
    Assignee: Mediatek Inc.
    Inventors: Chun-Ming Kuo, Wen-Chi Chao, Keng-Jan Hsiao, Song-Yu Yang, Chun-Chi Chen
  • Patent number: 8644781
    Abstract: A clock generator for a mobile device, capable of operating in one of a full-power mode and a low-power mode according to a standby signal to generate a high-frequency clock signal and a low-frequency clock signal is disclosed. The clock generator includes a crystal oscillator, for generating an oscillation signal of a specific frequency according to the power mode of the clock generator; a frequency division block, for dividing the oscillation signal by a specific divisor according to the power mode of the clock generator to generate the low-frequency clock signal; and a buffer block, for amplifying the oscillation signal to generate the high-frequency clock signal; wherein during each power mode, a frequency of the low-frequency clock signal is substantially the same.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: February 4, 2014
    Assignee: Mediatek Inc.
    Inventors: Chun-Ming Kuo, Song-Yu Yang
  • Publication number: 20130171953
    Abstract: A clock generator for a mobile device, capable of operating in one of a full-power mode and a low-power mode according to a standby signal to generate a high-frequency clock signal and a low-frequency clock signal is disclosed. The clock generator includes a crystal oscillator, for generating an oscillation signal of a specific frequency according to the power mode of the clock generator; a frequency division block, for dividing the oscillation signal by a specific divisor according to the power mode of the clock generator to generate the low-frequency clock signal; and a buffer block, for amplifying the oscillation signal to generate the high-frequency clock signal; wherein during each power mode, a frequency of the low-frequency clock signal is substantially the same.
    Type: Application
    Filed: June 12, 2012
    Publication date: July 4, 2013
    Inventors: Chun-Ming Kuo, Song-Yu Yang
  • Publication number: 20130169338
    Abstract: A clock generator utilized for providing a clock signal includes: a first oscillator and a switching circuit. The switching circuit is coupled to the first oscillator and a second oscillator, and utilized for receiving a first oscillating signal generated from the first oscillator and a second oscillating signal generated from the second oscillator, and selecting one of the first oscillating signal and the second oscillating signal as the clock signal according to a status signal.
    Type: Application
    Filed: June 13, 2012
    Publication date: July 4, 2013
    Inventors: Chun-Ming Kuo, Wen-Chi Chao, Keng-Jan Hsiao, Song-Yu Yang, Chun-Chi Chen
  • Patent number: 7978014
    Abstract: A digital PLL frequency synthesizer characterized by fast-locking and low-jitters is presented. The PLL comprises a phase detector, a controllable oscillator, a loop filter having an automatically-adjusted loop gain, a feedback phase integration circuit, and a reference phase integration circuit. Fast-locking is achieved by dynamically adjusting forward-path gain and integral-path gain according to the output of the phase detector and the output of the integral-path during phase tracking. A skew-compensated counter circuit is proposed, which incorporates an asynchronous counter, a data register and a sample phase generator and features high-speed and low-power operation.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: July 12, 2011
    Assignee: National Chiao Tung University
    Inventors: Wei-Zen Chen, Song-Yu Yang
  • Publication number: 20100039183
    Abstract: A digital PLL frequency synthesizer characterized by fast-locking and low-jitters is presented. The PLL comprises a phase detector, a controllable oscillator, a loop filter having an automatically-adjusted loop gain, a feedback phase integration circuit, and a reference phase integration circuit. Fast-locking is achieved by dynamically adjusting forward-path gain and integral-path gain according to the output of the phase detector and the output of the integral-path during phase tracking. A skew-compensated counter circuit is proposed, which incorporates an asynchronous counter, a data register and a sample phase generator and features high-speed and low-power operation.
    Type: Application
    Filed: March 16, 2009
    Publication date: February 18, 2010
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: WEI-ZEN CHEN, SONG-YU YANG