Abstract: A cell assembly according to the present disclosure includes a cell stack including one pouch-type battery cell or two or more pouch-type battery cells stacked; and a cell cover covering two side portions of the cell stack along a widthwise direction of the cell stack and a top portion of the cell stack, wherein the cell cover is configured to adjust a width of the cell cover according to a width of the cell stack.

Abstract: A magnetic memory device and a manufacturing method thereof are provided. The magnetic memory device can include a word line, a freely switchable layer, a fixed layer, a dielectric layer, and a bit line. The freely switchable layer can be electrically connected to a diffusion region at one side of the word line, and the fixed layer can be horizontally adjacent to the freely switchable layer. The dielectric layer can be provided between the freely switchable layer and the fixed layer, and the bit line can be electrically connected to the fixed layer.

Abstract: Disclosed is a semiconductor device that can be used as a high voltage transistor. The semiconductor device can include a gate electrode on a semiconductor substrate, drift regions in the substrate at opposite sides of the gate electrode, a source region in one of the drift regions and a drain region in the other of the drift regions, and a shallow trench isolation (STI) region in a portion of the drift region between the gate electrode and the drain region. The portion of the drift region below the STI region can have a doping profile in which the concentration of impurities decreases from the concentration at the lower surface of the STI region, and then increases, and then again decreases.

Abstract: A magnetic memory device and a manufacturing method thereof are provided. The magnetic memory device can include a word line, a freely switchable layer, a fixed layer, a dielectric layer, and a bit line. The freely switchable layer can be electrically connected to a diffusion region at one side of the word line, and the fixed layer can be horizontally adjacent to the freely switchable layer. The dielectric layer can be provided between the freely switchable layer and the fixed layer, and the bit line can be electrically connected to the fixed layer.

Abstract: A non-volatile memory device includes a semiconductor substrate having a plurality of trenches. A buried diffusion region may be formed in the substrate at one side of the trench. A gate insulating layer may be formed over the surface of the substrate. A floating gate may be formed over the gate insulating layer between the trenches. An insulating layer may be formed over the gate insulating layer and the floating gate. A control gate may be formed over the insulating layer.

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.