Abstract: The electrode comprises: a plurality of unit electrodes formed by connecting a plurality of electrodes made of an electrode mixture having a solid shape to each other; a separator interposed between the plurality of unit electrodes; and an electrode tab attached to the unit electrode, wherein the electrode tab comprises first and second electrode tabs, which are respectively attached to the unit electrodes and have different specific resistance.

Abstract: The present invention may provide an organic electroluminescent device which exhibits low driving voltage as well as high efficiency by including an electron transporting layer material having an improved electron transporting ability.

Abstract: A display device includes: a substrate including a first emission area, a second emission area, and a third emission area; a first wavelength conversion pattern overlapping the first emission area; a second wavelength conversion pattern overlapping the second emission area; and a light-transmitting pattern overlapping the third emission area, wherein the first wavelength conversion pattern includes first wavelength shifters configured to convert a first light into a second light, and first scatterers, the second wavelength conversion pattern includes second wavelength shifters configured to convert the first light into a third light, and second scatterers, and a ratio between a concentration of the first wavelength shifters and a concentration of the second wavelength shifters is 1:1.1 to 1:1.3.

Abstract: A semiconductor memory device including a device isolation layer in a substrate to define first and second active portions, a first contact on the substrate, first and second memory cells spaced apart from the first contact in a first direction by first and second distances, respectively, first and second conductive lines connected to the first and second memory cells, respectively, and extending in a second direction, and first and second selection transistors respectively connected to the first and second conductive lines. A length of a bottom surface of a first gate electrode of the first selection transistor overlapping the first active portion in a third direction may be different from a length of a bottom surface of a second gate electrode of the second selection transistor overlapping the second active portion in the third direction.

Abstract: A variable resistance memory device includes a memory cell structure on a substrate, the memory cell structure including conductive layers, each of the conductive layers including conductive lines spaced apart from each other in a direction parallel to a top surface of the substrate, and memory cell arrays alternatingly stacked with the conductive layers in a first direction perpendicular to a top surface of the substrate, a first peripheral circuit layer between the substrate and the memory cell structure, the first peripheral circuit layer including first transistors, and a second peripheral circuit layer between the first peripheral circuit layer and the memory cell structure, the second peripheral circuit layer including second transistors, and the second transistors including core transistors that are connected to corresponding ones of the conductive lines.

Abstract: A semiconductor device includes a substrate and memory cell arrays arranged on the substrate in a first direction and second direction. The first direction and second direction are parallel to a top surface of the substrate and intersect each other. The memory cell arrays include a plurality of memory cells. A cell dummy pattern on the substrate is arranged between the memory cell arrays in at least one of the first direction and second direction and extends along a side of the memory cell arrays. A cell conductive pattern is included on the substrate. A cell contact plug is configured to connect the cell dummy pattern and the cell conductive pattern. The cell contact plug is arranged between the cell dummy pattern and the cell conductive pattern in a third direction that is perpendicular to the first direction and the second direction.

Abstract: A semiconductor memory device is disclosed. The device may include a device isolation layer in a substrate to define first and second active portions, a first contact on the substrate, first and second memory cells spaced apart from the first contact in a first direction by first and second distances, respectively, first and second conductive lines connected to the first and second memory cells, respectively, and extending in a second direction, and first and second selection transistors respectively connected to the first and second conductive lines. A length of a bottom surface of a first gate electrode of the first selection transistor overlapping the first active portion in a third direction may be different from a length of a bottom surface of a second gate electrode of the second selection transistor overlapping the second active portion in the third direction.

Abstract: A semiconductor memory device includes: first conductive lines provided on a substrate and extending in a first direction in parallel, each of the first conductive lines including a first end portion and a second end portion that are opposite to each other, the first direction being parallel to a top surface of the substrate; first selection transistors respectively connected to the first end portions of the first conductive lines; and second selection transistors respectively connected to the second end portions of the first conductive lines. Each of the first selection transistors may have a first gate width. Each of the second selection transistors may have a second gate width smaller than the first gate width.

Abstract: A method of manufacturing a memory device includes forming a transistor on a substrate, forming a lower interlayer insulating layer covering the transistor, forming a hydrogen supply layer on the lower interlayer insulating layer, forming a hydrogen blocking layer on the hydrogen supply layer, annealing the transistor, the lower interlayer insulating layer, and the hydrogen supply layer, forming a memory cell on the hydrogen blocking layer after the annealing, and forming an upper interlayer insulating layer surrounding the memory cell and having a third average hydrogen concentration less than the second average hydrogen concentration.

Abstract: A tool steel having strength and high impact toughness incudes 0.7 to 0.9 wt % of C, 0.4 to 0.6 wt % of Si, 0.4 to 0.6 wt % of Mn, 7.0 to 9.0 wt % of Cr, 1.5 to 2.5 wt % of Mo, up to 1.0 wt % or less (excluding 0 wt %) of V, 0.01 to 0.06 wt % of Ce, and a remainder of Fe and inevitable impurities, wherein the tool steel has a hardness of 59 to 65 HRC and an impact toughness of 30 to 42 J/cm2. The tool steel has super-high-strength combined with high impact toughness due to inclusion of Ce, thus reducing primary carbide content in an as-cast state and after solution treatment and tempering.

Abstract: The present invention relates to a method for preparing a glutamate-based surfactant. More specifically, the present invention provides a method for preparing a glutamate-based surfactant, the method being very economical and being capable of mass production of the glutamate-based surfactant.

Abstract: A semiconductor device includes a substrate and memory cell arrays arranged on the substrate in a first direction and second direction. The first direction and second direction are parallel to a top surface of the substrate and intersect each other. The memory cell arrays include a plurality of memory cells. A cell dummy pattern on the substrate is arranged between the memory cell arrays in at least one of the first direction and second direction and extends along a side of the memory cell arrays. A cell conductive pattern is included on the substrate. A cell contact plug is configured to connect the cell dummy pattern and the cell conductive pattern. The cell contact plug is arranged between the cell dummy pattern and the cell conductive pattern in a third direction that is perpendicular to the first direction and the second direction.

Abstract: The present invention relates to a method for preparing a glutamate-based surfactant. More specifically, the present invention provides a method for preparing a glutamate-based surfactant, the method being very economical and being capable of mass production of the glutamate-based surfactant.

Abstract: According to an exemplary embodiment of the present inventive concept, a method of manufacturing a color conversion display panel includes forming a plurality of light blocking members on a substrate to partition a first region, a second region, and a third region. A blue light blocking filter is formed on the substrate of both the first region and the second region. A color conversion layer including quantum dots is formed on the blue light blocking filter. A transmissive layer is formed on the substrate of the third region. Water vapor is supplied to the color conversion layer, and a barrier layer is formed on the color conversion layer and the transmissive layer.

Abstract: Disclosed is super-high-strength tool steel having high impact toughness, including 0.7 to 0.9 wt % of C, 0.4 to 0.6 wt % of Si, 0.4 to 0.6 wt % of Mn, 7.0 to 9.0 wt % of Cr, 1.5 to 2.5 wt % of Mo, 1.0 wt % or less (excluding 0 wt %) of V, and at least one of 0.1 wt % or less (excluding 0 wt %) of Ti and 0.1 wt % or less (excluding 0 wt %) of Ce, with the remainder of Fe and inevitable impurities. The super-high-strength tool steel having high impact toughness includes at least one of Ti and Ce, thus reducing primary carbide content in an as-cast state and exhibiting improved impact toughness at a high hardness level after solution treatment and tempering. In addition, a method of manufacturing super-high-strength tool steel having improved impact toughness at a high hardness level is provided.

Abstract: A method of manufacturing a memory device includes forming a transistor on a substrate, forming a lower interlayer insulating layer covering the transistor, forming a hydrogen supply layer on the lower interlayer insulating layer, forming a hydrogen blocking layer on the hydrogen supply layer, annealing the transistor, the lower interlayer insulating layer, and the hydrogen supply layer, forming a memory cell on the hydrogen blocking layer after the annealing, and forming an upper interlayer insulating layer surrounding the memory cell and having a third average hydrogen concentration less than the second average hydrogen concentration.

Abstract: According to an exemplary embodiment of the present inventive concept, a method of manufacturing a color conversion display panel includes forming a plurality of light blocking members on a substrate to partition a first region, a second region, and a third region. A blue light blocking filter is formed on the substrate of both the first region and the second region. A color conversion layer including quantum dots is formed on the blue light blocking filter. A transmissive layer is formed on the substrate of the third region. Water vapor is supplied to the color conversion layer, and a barrier layer is formed on the color conversion layer and the transmissive layer.

Abstract: A plurality of first conductive patterns is disposed on a substrate. Each of the plurality of first conductive patterns extends in a first direction. A first selection pattern is disposed on each of the plurality of first conductive patterns. A first barrier portion surrounds the first selection pattern. A first electrode and a first variable resistance pattern are disposed on the first selection pattern. A plurality of second conductive patterns is disposed on the first variable resistance pattern. Each of the plurality of second conductive patterns extends in a second direction crossing the first direction.

Abstract: A plurality of first conductive patterns is disposed on a substrate. Each of the plurality of first conductive patterns extends in a first direction. A first selection pattern is disposed on each of the plurality of first conductive patterns. A first barrier portion surrounds the first selection pattern. A first electrode and a first variable resistance pattern are disposed on the first selection pattern. A plurality of second conductive patterns is disposed on the first variable resistance pattern.