Patents by Inventor Sonia Ghosh

Sonia Ghosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250095698
    Abstract: A random-access memory has its bitcells arranged into a first pair of banks and a second pair of banks. The first pair of banks and second pair of banks are separated by a central controller that contains sense amplifiers and write drivers for the first pair of banks and for the second pair of banks.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 20, 2025
    Inventors: Sonia GHOSH, Xiao CHEN, Chi-Jui CHEN
  • Publication number: 20240428831
    Abstract: A circuit is provided with a selectively diode-connected head switch transistor. During a light-sleep mode, the head switch transistor is diode connected so that a power supply voltage passing through the diode-connected head switch transistor is reduced by a transistor threshold voltage drop. During an active mode, the diode connection is opened so that the head switch transistor passes a power supply voltage with virtually no voltage drop.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 26, 2024
    Inventors: Chi-Jui CHEN, Xiao CHEN, Sonia GHOSH, Hochul LEE, Anil Chowdary KOTA, Giby SAMSON
  • Publication number: 20220102360
    Abstract: SRAM cell circuits have a minimum distance between a storage circuit active region and a read port circuit active region to reduce area. SRAM cell circuits are formed in FinFETs in a storage circuit active area and a read port active area each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bit cell has a reduced total area because a distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance of between 1.0 and 2.15 times the smallest center-to-center distance between adjacent fins. Minimizing a separation distance may include relocating a gate contact of a write access transistor from a location between the storage circuit active region and the read port active region to a location overlapping the storage circuit active area.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Inventors: Rahul Biradar, Sunil Sharma, Channappa Desai, Sonia Ghosh
  • Patent number: 11289495
    Abstract: SRAM cell circuits have a minimum distance between a storage circuit active region and a read port circuit active region to reduce area. SRAM cell circuits are formed in FinFETs in a storage circuit active area and a read port active area each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bit cell has a reduced total area because a distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance of between 1.0 and 2.15 times the smallest center-to-center distance between adjacent fins. Minimizing a separation distance may include relocating a gate contact of a write access transistor from a location between the storage circuit active region and the read port active region to a location overlapping the storage circuit active area.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 29, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Rahul Biradar, Sunil Sharma, Channappa Desai, Sonia Ghosh
  • Patent number: 11251123
    Abstract: Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines (WWL) for reduced memory write latency and improved memory write access performance, and related fabrication methods are disclosed. In exemplary aspects, the SRAM bit cell employs an increased width write word line based on a circuit cell layout area savings achieved by employing a reduced width read word line. Increasing the width of the write word line can reduce the resistance of the write word line and decrease memory write latency to the SRAM bit cell as a result. In certain exemplary aspects, the metal line pitch and minimum distance between metal lines of the SRAM bit cell can be maintained for maintaining fabrication compatibility with existing fabrication processes with decreasing the resistance of the write word line of the SRAM bit cell.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: February 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Sunil Sharma, Rahul Biradar, Sonia Ghosh
  • Patent number: 11222846
    Abstract: Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines (WWL) for reduced memory write latency and improved memory write access performance, and related fabrication methods are disclosed. In exemplary aspects, the SRAM bit cell employs an increased width write word line based on a circuit cell layout area savings achieved by employing a reduced width read word line. Increasing the width of the write word line can reduce the resistance of the write word line and decrease memory write latency to the SRAM bit cell as a result. In certain exemplary aspects, the metal line pitch and minimum distance between metal lines of the SRAM bit cell can be maintained for maintaining fabrication compatibility with existing fabrication processes with decreasing the resistance of the write word line of the SRAM bit cell.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 11, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Sunil Sharma, Rahul Biradar, Sonia Ghosh
  • Publication number: 20210255243
    Abstract: According to certain aspects, a method includes receiving an input test signal at a test input, receiving an event signal, and passing the input test signal to a test output or blocking the input test signal from the test output based on the event signal. In certain aspects, the event signal indicates an occurrence of an event in a circuit block (e.g., a memory, a processor, or another type of circuit block). The event may include a precharge operation, opening of input latches, reset of a self-time loop, arrival of a data value at a flop in a signal path, an interrupt signal indicating an error or failure in the circuit block, or another type of event.
    Type: Application
    Filed: February 18, 2020
    Publication date: August 19, 2021
    Inventors: Sonia GHOSH, Changho JUNG, Chulmin JUNG
  • Patent number: 11092646
    Abstract: According to certain aspects, a method includes receiving an input test signal at a test input, receiving an event signal, and passing the input test signal to a test output or blocking the input test signal from the test output based on the event signal. In certain aspects, the event signal indicates an occurrence of an event in a circuit block (e.g., a memory, a processor, or another type of circuit block). The event may include a precharge operation, opening of input latches, reset of a self-time loop, arrival of a data value at a flop in a signal path, an interrupt signal indicating an error or failure in the circuit block, or another type of event.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: August 17, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Sonia Ghosh, Changho Jung, Chulmin Jung
  • Patent number: 10916275
    Abstract: A method for operating a pseudo-dual port (PDP) memory is described. The method includes pre-charging bitline pairs BL and BLB coupled to unselected columns of the PDP memory according to a write operation during a pre-charge operation after a read operation of the PDP memory. The method also includes concurrently pulling-down a bitline pair BL and BLB coupled to a selected column of PDP memory according to the write operation.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: February 9, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Sonia Ghosh, Changho Jung
  • Patent number: 9905316
    Abstract: A memory includes a plurality of columns and a redundant column. The memory includes a plurality of multiplexers corresponding to the plurality of columns. Depending upon the location of a defect, the multiplexers are configured to select for their corresponding column or an immediately-subsequent column to their corresponding column.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: February 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Sonia Ghosh, Changho Jung
  • Publication number: 20180033495
    Abstract: A memory includes a plurality of columns and a redundant column. The memory includes a plurality of multiplexers corresponding to the plurality of columns. Depending upon the location of a defect, the multiplexers are configured to select for their corresponding column or an immediately-subsequent column to their corresponding column.
    Type: Application
    Filed: August 1, 2016
    Publication date: February 1, 2018
    Inventors: Sonia Ghosh, Changho Jung
  • Publication number: 20180012649
    Abstract: A memory is presented. The memory includes a plurality of memory cells, a wordline coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the sense amplifier. The timing circuit includes a delay stage and a dummy wordline. The dummy wordline is configured to emulate at least one portion of the wordline. An apparatus is presented. The apparatus include a first memory having a first wordline coupled to a first number of memory cells. A second memory having a second wordline coupled to a second number of memory cells. Each of the first memory and the second memory includes a timing circuit to enable a memory operation. The timing circuit includes a delay stage corresponding to loading of a third number of memory cells. The third number is different from the first number.
    Type: Application
    Filed: July 8, 2016
    Publication date: January 11, 2018
    Inventors: Sonia GHOSH, Changho JUNG
  • Patent number: 9858988
    Abstract: A memory is presented. The memory includes a plurality of memory cells, a wordline coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the sense amplifier. The timing circuit includes a delay stage and a dummy wordline. The dummy wordline is configured to emulate at least one portion of the wordline. An apparatus is presented. The apparatus include a first memory having a first wordline coupled to a first number of memory cells. A second memory having a second wordline coupled to a second number of memory cells. Each of the first memory and the second memory includes a timing circuit to enable a memory operation. The timing circuit includes a delay stage corresponding to loading of a third number of memory cells. The third number is different from the first number.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: January 2, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Sonia Ghosh, Changho Jung
  • Patent number: 9685210
    Abstract: A memory includes a plurality of memory cells and a plurality of bitlines. Each of the plurality of bitlines is coupled to a corresponding one of the plurality of memory cells. A precharge circuit precharges each of the plurality of bitlines before a read operation and precharges all but one of the plurality of bitlines following the read operation. A write driver drives the one of the plurality of bitlines following the read operation. A method includes precharging each of a plurality of bitlines before a read operation. Each of the plurality of bitlines is coupled to a corresponding one of a plurality of memory cells. The method further includes precharging all but one of the plurality of bitlines following the read operation and driving the one of the plurality of bitlines following the read operation.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 20, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Sonia Ghosh, Changho Jung
  • Patent number: 9564375
    Abstract: Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: February 7, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Randy Mann, Sandeep Puri, Sonia Ghosh, Anuj Gupta, Xusheng Wu
  • Patent number: 9484300
    Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sonia Ghosh, Randy Mann, Norman Chen, Shaowen Gao
  • Publication number: 20160093565
    Abstract: Methods for forming a semiconductor layer, such as a metal 1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 31, 2016
    Inventors: Sonia GHOSH, Randy MANN, Norman CHEN, Shaowen GAO
  • Patent number: 9263349
    Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sonia Ghosh, Randy Mann, Norman Chen, Shaowen Gao
  • Publication number: 20150130026
    Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Sonia GHOSH, Randy MANN, Norman CHEN, Shaowen GAO
  • Publication number: 20150102826
    Abstract: Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Randy MANN, Sandeep PURI, Sonia GHOSH, Anuj GUPTA, Xusheng WU