Abstract: Embodiments of the instant invention relate to a system for maintaining the integrity of data transfers in shared memory configuration by different processes to a data buffer located in the contiguous memory locations. The accesses by the different processes can be at the same time. One embodiment employs a CISC CPU, a peripheral using Direct Memory Access (DMA) controller both of which has a 8-bit data bus. The Memory Interface is provided with a sequencer and registers coupled to a Random Access Memory (RAM). The sequencer controls read and write operations of the RAM and ensures atomic transfer of multiple bytes to the RAM by one process invoking a special mode. This ensures that the other processes either read the old set of data or the new set of data with a minimum delay.

Abstract: An area efficient system for providing serial access of multiple data buffers to a data retaining and processing device. The system includes a first circuit to synchronize a clock signal and a data signal and a data retaining and processing device to receive data from said data bus to thereby generate a status signal indicating the receipt of data by said area efficient system; a reference bus address and said data bus. The system also includes a device to compare the reference bus address with the content of memory for generating an address matching signal and a control signal generator to govern the data write signal generation for said shifting means. The system further includes a sequencer to read and write data from/to said data retaining and processing device in a plurality of subcycles for efficiently accessing storage buffers and a direct storage access controlling means for generating interrupt signals and access request signals.