Abstract: An improved low inductance termination scheme is disclosed for grid array capacitors. The enhanced termination scheme provides for shorter termination length and leaves the sides of a capacitive element free from any structure. The area typically taken up by solder lands is reduced, facilitating much closer chip spacing on a circuit board. The arrangement generally includes interleaved dielectric and electrode layers in an interdigitated configuration. Vias are drilled through tabs extending from selected of the electrode layers, and then filled with suitable conductive material. Solder balls may be applied directly to this conductive material, providing a ball grid array (BGA) packaged chip ready to mount on an IC and reflow. Composition of such solder balls is easily varied to comply with specific firing conditions. Such capacitor chips are also compatible with land grid array (LGA) packaging techniques.

Abstract: A method of manufacturing solid state capacitors involves providing an elongate band of solid state forming metal, folding the band into a trough-like U-shaped configuration, introducing a layer of solid state metal powder into the trough, sintering the powdered metal to thereby bond the metal to the foil, partially severing the foil and sintered powder to define a multiplicity of individual units which are thereafter processed to convert the units into capacitors by sequential dielectric forming and counterelectrode depositing steps. The individual capacitors are terminated and preferably also may be tested while still interconnected by portions of the foil, following which individual capacitors are separated by cuts which register with the initial cuts which defined the individual units. The disclosure further teaches a novel solid state capacitor fabricated in accordance with the method, the capacitor exhibiting high volumetric efficiency and being particularly adapted for surface mounting.