Patents by Inventor Sonja Koller

Sonja Koller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200365996
    Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a cavity resonator antenna over the first conductive layer and substrate. The cavity resonator antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the cavity resonator antenna, first conductive layer, and substrate. The conductive cavity may extend vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Inventors: Kilian ROTH, Sonja KOLLER, Josef HAGN, Andreas WOLTER, Andreas AUGUSTIN
  • Publication number: 20200352035
    Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-rid array. The ball-grid array can at least partially penetrate the printed wiring-board island.
    Type: Application
    Filed: September 29, 2017
    Publication date: November 5, 2020
    Inventors: Georg Seidemann, Sonja Koller, Bernd Waidhas
  • Publication number: 20200227388
    Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 16, 2020
    Inventors: Bernd Waidhas, Georg Seidemann, Thomas Wagner, Andreas Wolter, Andreas Augustin, Sonja Koller, Thomas Ort, Reinhard Mahnkopf
  • Patent number: 10658201
    Abstract: A method for forming a carrier substrate for a semiconductor device, the method includes providing a substrate layer including conductive particles embedded in an electrically insulating material and localized heating of the substrate layer along a desired trace by a laser to form a conductive trace of merged particles along the desired trace.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: May 19, 2020
    Assignee: Intel IP Corporation
    Inventors: Sonja Koller, Georg Seidemann, Bernd Waidhas
  • Patent number: 10651102
    Abstract: An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 12, 2020
    Assignee: Intel IP Corporation
    Inventors: Klaus Reingruber, Christian Geissler, Georg Seidemann, Sonja Koller
  • Publication number: 20200144723
    Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.
    Type: Application
    Filed: March 31, 2017
    Publication date: May 7, 2020
    Inventors: Andreas Augustin, Sonja Koller, Bernd Waidhas, Georg Seidemann, Andreas Wolter, Stephan Stoeckl, Thomas Wagner, Josef Hagn
  • Patent number: 10629731
    Abstract: A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 21, 2020
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Sonja Koller, Georg Seidemann
  • Publication number: 20200111607
    Abstract: A recess in a die backside surface occupies a footprint that accommodates an inductor coil that is formed in metallization above an active surface of the die. Less semiconductive material is therefore close to the inductor coil. A ferromagnetic material is formed in the recess, or a ferromagnetic material is formed on a dielectric layer above the inductor coil. The recess may extend across a die that allows the die to be deflected at the recess.
    Type: Application
    Filed: March 30, 2017
    Publication date: April 9, 2020
    Inventors: Andreas Augustin, Bernd Waidhas, Sonja Koller, Reinhard Mahnkopf, Georg Seidemann
  • Publication number: 20200043826
    Abstract: A system-in-package apparatus includes a contoured heat sink that provides a first recess and a subsequent recess. The system-in-package apparatus includes a flexible printed wiring board that is wrapped onto the contoured heat sink after a manner to enclose the first semiconductive device into the first recess and a semiconductive device in the subsequent recess.
    Type: Application
    Filed: December 30, 2016
    Publication date: February 6, 2020
    Applicant: Intel IP Corporation
    Inventors: Sonja Koller, Reinhard Mahnkopf
  • Patent number: 10535578
    Abstract: A semiconductor device includes a plurality of circuit regions formed at a circuit semiconductor layer of a semiconductor die. The semiconductor device includes an etch stop layer of the semiconductor die arranged between the circuit semiconductor layer of the semiconductor die and a handling layer of the semiconductor die. The semiconductor device includes one or more trench structures extending through the handling layer of the semiconductor die. The one or more trench structures extends to at least the etch stop layer and to at most the circuit semiconductor layer of the semiconductor die.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 14, 2020
    Assignee: Intel IP Corporation
    Inventors: Reinhard Mahnkopf, Andreas Wolter, Sonja Koller
  • Publication number: 20190393125
    Abstract: Present disclosure relates to IC packages with integrated thermal contacts. In some embodiments, an IC package includes a package substrate, an IC die that is coupled to the package substrate, and at least one thermal contact for coupling to at least a portion of a heat exchanger, where the thermal contact is limited to being in a region located at a periphery of the IC package. In some embodiments, thermal contacts are such that at least a portion of a heat exchanger is to be attached on the side of the IC package. In some embodiments, thermal contacts may be provided within a recessed portion at the periphery of the IC package. Providing a thermal contact at a periphery of an IC package may enable improved cooling options, especially for systems where there is no or limited space for providing conventional heat exchangers on the top of the package.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Applicant: Intel IP Corporation
    Inventors: Sonja Koller, Vishnu Prasad, Georg Seidemann
  • Publication number: 20190393130
    Abstract: Present disclosure relates to IC devices with thermal mitigation structures in the form of metal structures provided in a semiconductor material of a substrate on which active electronic devices are integrated (i.e., front-end metal structures). In one aspect, an IC device includes a substrate having a first face and a second face, where at least one active electronic device is integrated at the first face of the substrate. The IC device further includes at least one front-end metal structure that extends from the first face of the substrate into the substrate to a depth that is smaller than a distance between the first face and the second face. Providing front-end metal structures may enable improved cooling options because such structures may be placed in closer vicinity to the active electronic devices, compared to conventional thermal mitigation approaches.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Applicant: Intel IP Corporation
    Inventors: Reinhard Mahnkopf, Sonja Koller, Andreas Wolter
  • Publication number: 20190297758
    Abstract: An electromagnetic shielding cap for shielding an electrical circuit on a circuit board includes a frame structure and a lid structure containing a passive electrical element structure. The lid structure is attached to the frame structure and further contains at least one contact interface for connecting the passive electrical element structure to an electrical circuit to be shielded by the electromagnetic shielding cap.
    Type: Application
    Filed: March 23, 2018
    Publication date: September 26, 2019
    Inventors: Sonja KOLLER, Saravana MARUTHAMUTHU, Bernd WAIDHAS
  • Publication number: 20190295857
    Abstract: A method for forming a carrier substrate for a semiconductor device, the method includes providing a substrate layer including conductive particles embedded in an electrically insulating material and localized heating of the substrate layer along a desired trace by a laser to form a conductive trace of merged particles along the desired trace.
    Type: Application
    Filed: March 26, 2018
    Publication date: September 26, 2019
    Inventors: Sonja Koller, Georg Seidemann, Bernd Waidhas
  • Publication number: 20190267312
    Abstract: A system-in-package apparatus includes a square wave lead frame that provides a recess for a first semiconductive device as well as a feature for a second device. The system-in-package apparatus includes a printed wiling board that is wrapped onto the lead frame after a manner to enclose the first semiconductive device into the recess.
    Type: Application
    Filed: December 29, 2016
    Publication date: August 29, 2019
    Inventors: Sonja Koller, Georgg Seidemann, Reinhard Mahnkopf, Bernd Waidhas
  • Patent number: 10373844
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: August 6, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Sven Albers, Sonja Koller, Thorsten Meyer, Georg Seidemann, Christian Geissler, Andreas Wolter
  • Publication number: 20190214327
    Abstract: A semiconductor device includes a semiconductor die that is coupled to a substrate. A mold compound encapsulates the semiconductor die and one or more passages are in the mold compound between a backside of the mold compound and an electrically non-active region of the first semiconductor die. A thermal conductor material within the one or more of the passages.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Inventors: Sonja Koller, Bernd Waidhas, Thomas Ort, Andreas Wolter
  • Patent number: 10347558
    Abstract: Embodiments herein generally relate to the field of package assembly to facilitate thermal conductivity. A package may have a hanging die, and attach to a printed circuit board (PCB). The package may have an active side plane and an inactive side plane opposite the first active side plane. The package may also have a ball grid array (BGA) matrix having a height determined by a distance of a furthest point of the BGA matrix from the active side plane of the package. The package may have a hanging die attached to the active side plane of the package, the hanging die having a z-height greater than the BGA matrix height. When package is attached to the PCB, the hanging die may fit into an area on the PCB that is recessed or has been cut away, and a thermal conductive material may connect the hanging die and the PCB.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 9, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Christian Geissler, Georg Seidemann, Sonja Koller, Jan Proschwitz
  • Publication number: 20190207027
    Abstract: A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Bernd Waidhas, Sonja Koller, Georg Seidemann
  • Publication number: 20190206777
    Abstract: An interposer for an electronic package including at least one angled via. The interposer can include a dielectric layer including a first surface and a second surface. The dielectric layer can include a normal axis perpendicular with the first or second surface. In an example, an angled via can include a first end located along the first surface and a second end located along the second surface. A longitudinal axis of the angled via can be extended between the first end and the second end. The longitudinal axis is disposed at an angle from the normal axis to form an angled via.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Sonja Koller, Lizabeth Keser, Bernd Waidhas, Georg Seidmann