Abstract: Embodiments of a microelectronic assembly comprises a first layer, a second layer and a third layer in a stack; a package substrate in the first layer, the package substrate comprising a metallic via structure; a first integrated circuit (IC) die surrounded by an organic dielectric material in the second layer, the first IC die coupled to the package substrate; a second IC die in the third layer, the second IC die coupled to the first IC die; and a third IC die in the third layer, the third IC die coupled to the first IC die. An electrically conductive pathway in the first IC die electrically couples the third IC die and the second IC die, and the first IC die is coupled to the package substrate with a thermally conductive material in contact with the metallic via structure in the package substrate.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a surface including a first cavity; a first die at least partially nested in the first cavity and electrically coupled to the substrate; and a circuit board having a surface including a second cavity, wherein the surface of the substrate is electrically coupled to the surface of the circuit board, and wherein the first die extends at least partially into the second cavity in the circuit board.

Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.

Abstract: Embodiments of a microelectronic assembly comprise a package substrate, including: a first layer comprising a first plurality of mutually parallel channels of a first material; a second layer comprising columns of the first material; and a third layer comprising a second plurality of mutually parallel channels of the first material. The second layer is between the first layer and the third layer, at least some columns extend between and contact the first plurality of mutually parallel channels and the second plurality of mutually parallel channels, and at least a portion of the first layer, the second layer, and the third layer comprises a second material different from the first material.

Abstract: Embodiments of a microelectronic assembly include a package substrate comprising: a first layer comprising a first plurality of mutually parallel channels of a first material; a second layer comprising columns of the first material; and a third layer comprising a second plurality of mutually parallel channels of the first material, the second plurality of mutually parallel channels being orthogonal to the first plurality of mutually parallel channels. The second layer is between the first layer and the third layer, at least some columns extend between and contact the first plurality of mutually parallel channels and the second plurality of mutually parallel channels, and at least a portion of the first layer, the second layer and the third layer comprises a second material different from the first material.

Abstract: A present chip assembly may have a matrix of dies and cooling devices that may provide active cooling within a package. The cooling devices may provide airflow directed to spaces that are provided between dies placed on a support platform. The placement of the cooling devices may be optimized to provide active cooling at hot spot areas of the package.

Abstract: The present disclosure relates to an assembly for preventing warpage in a semiconductor package. The assembly may include a semiconductor package substrate including one or more channels arranged longitudinally in an inner core layer of the semiconductor package substrate. The assembly may further include a mount assembly including one or more mounts operable to be insertable into corresponding channels of the semiconductor package substrate.

Abstract: A device may include a carrier with a plurality of first bump pads. The device may include a first die with a plurality of second bump pads. The device may include a plurality of first bumps disposed between the plurality of first bump pads and the plurality of second bump pads to electrically connect the first die to the carrier. The device may include solder disposed between the plurality of first bump pads and the plurality of second bump pads, wherein the plurality of first bump pads have a first pitch relative to one another, and the plurality of second bump pads have a second pitch relative to one another, and wherein the first pitch is different from the second pitch. Each first bump pad of the plurality of first bump pads is larger than each second bump pad of the plurality of second bump pads.

Abstract: A semiconductor tool having a support assembly for holding a semiconductor panel in a level position during an assembly process is able to remediate the warpage that may be present in the semiconductor panel. The support assembly may be equipped with a plurality of height-adjustable support pillars in the form of an array that is positioned below the semiconductor panel to provide a level position. The support pillars may be activated by a controller to engage or land on dedicated landing features or pads formed on the semiconductor panel or on suitable landing features that may be found in a semiconductor design layout and provide a dual use.

Abstract: Present disclosure relates to IC packages with integrated thermal contacts. In some embodiments, an IC package includes a package substrate, an IC die that is coupled to the package substrate, and at least one thermal contact for coupling to at least a portion of a heat exchanger, where the thermal contact is limited to being in a region located at a periphery of the IC package. In some embodiments, thermal contacts are such that at least a portion of a heat exchanger is to be attached on the side of the IC package. In some embodiments, thermal contacts may be provided within a recessed portion at the periphery of the IC package. Providing a thermal contact at a periphery of an IC package may enable improved cooling options, especially for systems where there is no or limited space for providing conventional heat exchangers on the top of the package.

Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.

Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.

Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a first surface including a cavity and an opposing second surface; a die above the cavity and electrically coupled to the second surface of the substrate; a circuit board attached to the substrate; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die. In some embodiments, a microelectronic assembly may include a circuit board having a surface including a cavity; a substrate having a first surface attached to the circuit board and a die electrically coupled to an opposing second surface; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die.

Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a surface including a first cavity; a first die at least partially nested in the first cavity and electrically coupled to the substrate; and a circuit board having a surface including a second cavity, wherein the surface of the substrate is electrically coupled to the surface of the circuit board, and wherein the first die extends at least partially into the second cavity in the circuit board.

Abstract: Embodiments of a microelectronic assembly comprises a first layer, a second layer and a third layer in a stack; a package substrate in the first layer, the package substrate comprising a metallic via structure; a first integrated circuit (IC) die surrounded by an organic dielectric material in the second layer, the first IC die coupled to the package substrate; a second IC die in the third layer, the second IC die coupled to the first IC die; and a third IC die in the third layer, the third IC die coupled to the first IC die. An electrically conductive pathway in the first IC die electrically couples the third IC die and the second IC die, and the first IC die is coupled to the package substrate with a thermally conductive material in contact with the metallic via structure in the package substrate.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.

Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.