Abstract: A delay device includes storage elements arranged in at least two rows 4, 5; 6, 7 in an integrated circuit, preferably in switched-capacitor technology. The delay device 2; 3 has an even number of storage elements. A first clock signal is provided from which, for producing a delay time equal to an odd multiple of the clock period of the first clock signal, a second clock signal is derived by means of a clock generation circuit 9, this second clock signal clocking the storage elements and being derived from the first clock signal in such a manner that one clock pulse of the first clock signal is suppressed in a selectable or given cycle and all the other clock pulses in the cycle are taken over in the second clock signal.

Abstract: A comb filter arrangement comprising at least one delay circuit and an adder, this adder being twice supplied with a video signal modulated on a carrier, which video signals are applied mutually shifted with time. The signals are delayed by the delay circuits, so that either video signal applied to the adder is delayed relative to the other video signal by a given period of time. Furthermore, the delay circuits are arranged in switched capacitor technique.

Abstract: For activating or deactivating the comb filter function with pixel precision, a comb filter arrangement including a delay circuit (3) and a first matching circuit (1) having at least two storage cells, these circuits receive a picture signal, having a sequence of individual pixels applied to the comb filter arrangement. The output signals of the delay circuit and the first matching circuit are superposed by a superposition stage (4) supplying a filtered picture signal from its output. The matching circuit (1) is implemented in such a way that it gives the picture signal applied thereto substantially the same amplitude variations as the delay circuit (3), and that the difference between the delay of the output signals from the delay circuit (3) and the matching circuit (1) corresponds to a nominal value.

Abstract: A delay circuit having at least two memory cells (3, 4, 5, 6, 8, 9) each including a capacitive memory element (20, 26, 40, 45), a write transistor (22, 28, 42, 47) by which information to be delayed can be written from a write line (18) into the capacitive memory element (20, 26, 40, 45), and a read transistor (21, 27, 41, 46) by which information can be read from the capacitive memory element (20, 26, 40, 45) on a read line (19), and having a control arrangement which is clocked by means of a first control clock and whose input receives a control signal and which includes intercoupled control circuits (11, 12, 13, 14, 15, 16) one of which is associated with a respective memory cell (3, 4, 5, 6, 8, 9), each control circuit (11, 12, 13, 14, 15, 16) of the read transistor (21, 27, 41, 46) of the associated memory cell (3, 4, 5, 6, 8, 9) being controllable by means of the input signal and each control circuit (11, 12, 13, 14, 15, 16) of the write transistor (22, 28, 42, 47) of the associated memory cell being c