Patents by Inventor Sonny E. Williams

Sonny E. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8656109
    Abstract: A system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. Also provided are physical computer storage mediums including a computer program product for performing the above method.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
  • Patent number: 8639888
    Abstract: A system includes a cache and a processor. The processor is configured to utilize a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilize a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time. One method includes utilizing a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilizing a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Sonny E. Williams
  • Patent number: 8595433
    Abstract: A system includes a cache partitioned into multiple ranks configured to store multiple storage tracks and a processor coupled to the cache. The processor is configured to perform the following method. One method includes allocating an amount of storage space in the cache to each rank and monitoring a current amount of storage space used by each rank with respect to the amount of storage space allocated to each respective rank. The method further includes destaging storage tracks from each rank until the current amount of storage space used by each respective rank is equal to a predetermined minimum amount of storage space with respect to the amount of storage space allocated to each rank.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
  • Patent number: 8589623
    Abstract: A system includes a cache and a processor. The processor is configured to utilize a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilize a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time. One method includes utilizing a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilizing a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Sonny E. Williams
  • Patent number: 8589624
    Abstract: A system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
  • Patent number: 8566518
    Abstract: Write caching for sequential tracks is performed by a processor device in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit. If a first track is determined to be sequential, and an earlier track is also determined to be sequential, a temporal bit associated with the earlier track is cleared to allow for destage of data of the earlier track. If a temporal bit for one of a plurality of additional tracks in one of a plurality of strides in a modified cache is determined to be not set, a stride associated with the one of the plurality of additional tracks is selected for a destage operation. If the NVS exceeds a predetermined storage threshold, a predetermined one of the plurality of strides is selected for the destage operation.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Joseph S. Hyde, II, Sonny E. Williams
  • Patent number: 8566535
    Abstract: A system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes writing data to the plurality of storage tracks and incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes scan each of the storage tracks in each of multiple scan cycles, decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Sonny E. Williams
  • Patent number: 8549220
    Abstract: Method, system, and computer program product embodiments for, in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit, identifying working data on a stride basis by a processor device are provided. A multi-update bit is established for each of a plurality of strides in a modified cache, wherein the multi-update bit is adapted to indicate a corresponding stride is part of at least one track in a working set that refers to a group of frequently updated tracks. The plurality of strides are scanned based on a schedule to identify tracks for destaging. An operation to destage is performed on a selected track identified during the scanning, if the multi-update bit of a selected stride on the selected track is set to indicate the selected track is part of the working set and if the NVS is about 90% full or greater.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Joseph S. Hyde, II, Sonny E. Williams
  • Publication number: 20130198752
    Abstract: For increased destaging efficiency by smoothing destaging tasks to reduce long input/output (I/O) read operations in a computing environment, destaging tasks are calculated according to one of a standard time interval and a variable recomputed destaging task interval. The destaging of storage tracks between a desired number of destaging tasks and a current number of destaging tasks is smoothed according to the calculating.
    Type: Application
    Filed: June 29, 2012
    Publication date: August 1, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. BENHASE, Lokesh M. GUPTA, Roger G. HATHORN, Sonny E. WILLIAMS
  • Publication number: 20130198751
    Abstract: For increased destaging efficiency by smoothing destaging tasks to reduce long input/output (I/O) read operations in a computing environment, destaging tasks are calculated according to one of a standard time interval and a variable recomputed destaging task interval. The destaging of storage tracks between a desired number of destaging tasks and a current number of destaging tasks is smoothed according to the calculating.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. BENHASE, Lokesh M. GUPTA, Roger G. HATHORN, Sonny E. WILLIAMS
  • Patent number: 8443141
    Abstract: Write caching for sequential tracks is performed by a processor device in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit. If a first track is determined to be sequential, and an earlier track is also determined to be sequential, a temporal bit associated with the earlier track is cleared to allow for destage of data of the earlier track. If a temporal bit for one of a plurality of additional tracks in one of a plurality of strides in a modified cache is determined to be not set, a stride associated with the one of the plurality of additional tracks is selected for a destage operation. If the NVS exceeds a predetermined storage threshold, a predetermined one of the plurality of strides is selected for the destage operation.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: May 14, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Joseph S. Hyde, II, Sonny E. Williams
  • Publication number: 20130007372
    Abstract: Method, system, and computer program product embodiments for, in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit, identifying working data on a stride basis by a processor device are provided. A multi-update bit is established for each of a plurality of strides in a modified cache, wherein the multi-update bit is adapted to indicate a corresponding stride is part of at least one track in a working set that refers to a group of frequently updated tracks. The plurality of strides are scanned based on a schedule to identify tracks for destaging. An operation to destage is performed on a selected track identified during the scanning, if the multi-update bit of a selected stride on the selected track is set to indicate the selected track is part of the working set and if the NVS is about 90% full or greater.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent C. BEARDSLEY, Michael T. BENHASE, Lokesh M. GUPTA, Joseph S. HYDE, II, Sonny E. WILLIAMS
  • Patent number: 8332589
    Abstract: Method, system, and computer program product embodiments for, in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit, identifying working data on a stride basis by a processor device are provided. A multi-update bit is established for each stride in a modified cache. The multi-update bit is adapted to indicate at least one track in a working set. A schedule of destage scans is configured based on a plurality of levels of urgency. A destage operation is performed based on at least one of a number of strides examined by the destage scans, whether the multi-update bit is set, and whether an emergency level of the plurality of levels of urgency is active.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Joseph S. Hyde, II, Sonny E. Williams
  • Publication number: 20120260044
    Abstract: A system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes writing data to the plurality of storage tracks and incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes scan each of the storage tracks in each of multiple scan cycles, decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 11, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent C. BEARDSLEY, Michael T. BENHASE, Lokesh M. GUPTA, Sonny E. WILLIAMS
  • Publication number: 20120254539
    Abstract: A system includes a cache and a processor. The processor is configured to utilize a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilize a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time. One method includes utilizing a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilizing a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent C. BEARDSLEY, Michael T. BENHASE, Lokesh M. GUPTA, Sonny E. WILLIAMS
  • Publication number: 20120254544
    Abstract: A system includes a cache partitioned into multiple ranks configured to store multiple storage tracks and a processor coupled to the cache. The processor is configured to perform the following method. One method includes allocating an amount of storage space in the cache to each rank and monitoring a current amount of storage space used by each rank with respect to the amount of storage space allocated to each respective rank. The method further includes destaging storage tracks from each rank until the current amount of storage space used by each respective rank is equal to a predetermined minimum amount of storage space with respect to the amount of storage space allocated to each rank.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent C. BEARDSLEY, Michael T. BENHASE, Binny S. GILL, Lokesh M. GUPTA, Sonny E. WILLIAMS
  • Publication number: 20120254545
    Abstract: A system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent C. BEARDSLEY, Michael T. BENHASE, Binny S. GILL, Lokesh M. GUPTA, Sonny E. WILLIAMS
  • Publication number: 20120233408
    Abstract: Write caching for sequential tracks is performed by a processor device in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit. If a first track is determined to be sequential, and an earlier track is also determined to be sequential, a temporal bit associated with the earlier track is cleared to allow for destage of data of the earlier track. If a temporal bit for one of a plurality of additional tracks in one of a plurality of strides in a modified cache is determined to be not set, a stride associated with the one of the plurality of additional tracks is selected for a destage operation. If the NVS exceeds a predetermined storage threshold, a predetermined one of the plurality of strides is selected for the destage operation.
    Type: Application
    Filed: May 23, 2012
    Publication date: September 13, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent C. BEARDSLEY, Michael T. BENHASE, Lokesh M. GUPTA, Joseph S. HYDE, II, Sonny E. WILLIAMS
  • Publication number: 20120151140
    Abstract: Systems and methods for destaging storage tracks from cache are provided. One system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes writing data to the plurality of storage tracks and incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes scan each of the storage tracks in each of multiple scan cycles, decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count. Also provided are physical computer storage mediums including a computer program product for performing the above method.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 14, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent C. BEARDSLEY, Michael T. BENHASE, Lokesh M. GUPTA, Sonny E. WILLIAMS
  • Publication number: 20120151148
    Abstract: Systems and methods for background destaging storage tracks from cache when one or more hosts are idle are provided. One system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. Also provided are physical computer storage mediums including a computer program product for performing the above method.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 14, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent C. BEARDSLEY, Michael T. BENHASE, Binny S. GILL, Lokesh M. GUPTA, Sonny E. WILLIAMS