Abstract: A method and system of accelerating monitoring of network traffic. The method may include receiving, at a network chip of a network device, a network traffic data unit; capturing, by the network chip, the network traffic data unit based on a traffic sampling rate; adding, by the network chip, a sampling header to the network traffic data unit to obtain a sampled network traffic data unit; sending the sampled network traffic data unit from the network chip to a sampling engine; receiving, from the sampling engine, a flow datagram that includes a network traffic data unit portion and a flow datagram header; generating a flow network data traffic unit that includes the flow datagram; and transmitting the flow network data traffic unit towards a collector.

Abstract: A method and system of accelerating monitoring of network traffic. The method may include receiving, at a network chip of a network device, a network traffic data unit; capturing, by the network chip, the network traffic data unit based on a traffic sampling rate; adding, by the network chip, a sampling header to the network traffic data unit to obtain a sampled network traffic data unit; sending the sampled network traffic data unit from the network chip to a sampling engine; receiving, from the sampling engine, a flow datagram that includes a network traffic data unit portion and a flow datagram header; generating a flow network data traffic unit that includes the flow datagram; and transmitting the flow network data traffic unit towards a collector.

Abstract: A method and system for reordering data units that are to be written to, or read from, selected locations in a memory are described herein. The data units are reordered so that an order of accessing memory is optimal for speed of reading or writing memory, not necessarily an order in which data units were received or requested. Packets that are received at input interfaces are divided into cells, with cells being allocated to independent memory banks. Many such memory banks are kept busy concurrently, so cells (and thus the packets) are read into the memory as rapidly as possible. The system may include an input queue for receiving data units in a first sequence and a set of storage queues coupled to the input queue for receiving data units from the input queue. The data units may be written from the storage queues to the memory in an order other than the first sequence.