Patents by Inventor Sonoe Matsushita

Sonoe Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor storage device and method for manufacturing semiconductor storage device
    Patent number: 11037948
    Abstract: A semiconductor storage device according to one embodiment is the semiconductor storage device that includes: a cell array region having a plurality of memory cells; and an outer edge portion arranged at an end portion to surround the cell array region. A stacked body in which a plurality of conductive layers are stacked via a first insulating layer and which has a stair portion in which end portions of the plurality of conductive layers form a stair shape is provided inside the cell array region, the stair portion facing the outer edge portion. A center of at least one step of the stair portion has a recess directed to an inner side of the cell array region.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: June 15, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Sonoe Matsushita, Takahito Nishimura, Kazuyuki Yoshimochi, Yoshihiro Yanai, Satoshi Usui
  • SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STORAGE DEVICE
    Publication number: 20200295022
    Abstract: A semiconductor storage device according to one embodiment is the semiconductor storage device that includes: a cell array region having a plurality of memory cells; and an outer edge portion arranged at an end portion to surround the cell array region. A stacked body in which a plurality of conductive layers are stacked via a first insulating layer and which has a stair portion in which end portions of the plurality of conductive layers form a stair shape is provided inside the cell array region, the stair portion facing the outer edge portion. A center of at least one step of the stair portion has a recess directed to an inner side of the cell array region.
    Type: Application
    Filed: September 5, 2019
    Publication date: September 17, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Sonoe Matsushita, Takahito Nishimura, Kazuyuki Yoshimochi, Yoshihiro Yanai, Satoshi Usui