Abstract: Disclosed is a convergence machining apparatus based on turning in which a rotational axis of a work piece fixed by a headstock and a tailstock and a center of a width of a slide surface of a bed on which a reciprocal carriage installed with a tool is transferred while being supported are positioned at the same virtual plane, thereby preventing an offset error according to a relative displacement between the work piece and the tool during processing.

Abstract: Disclosed is a convergence machining apparatus based on turning in which a rotational axis of a work piece fixed by a headstock and a tailstock and a center of a width of a slide surface of a bed on which a reciprocal carriage installed with a tool is transferred while being supported are positioned at the same virtual plane, thereby preventing an offset error according to a relative displacement between the work piece and the tool during processing.

Abstract: The present invention relates to a stage with a displacement measuring means capable of measuring a displacement, and more particularly, to a stage provided with a displacement magnification means capable of magnifying a displacement so as to precisely measure a minute displacement on the order of nanometers. A stage according to an aspect of the present invention comprises a fixed base, a movable table, a first elastic support, a first actuator, a first displacement converting means and a first displacement measuring means. The movable table is installed to be movable with respect to the fixed base. The first elastic support supports the movable table with respect to the fixed base, and the first actuator generates a displacement of the movable table in one direction.

Abstract: The present invention relates to a stage with a displacement measuring means capable of measuring a displacement, and more particularly, to a stage provided with a displacement magnification means capable of magnifying a displacement so as to precisely measure a minute displacement on the order of nanometers. A stage according to an aspect of the present invention comprises a fixed base, a movable table, a first elastic support, a first actuator, a first displacement converting means and a first displacement measuring means. The movable table is installed to be movable with respect to the fixed base. The first elastic support supports the movable table with respect to the fixed base, and the first actuator generates a displacement of the movable table in one direction.

Abstract: The present invention provide an CMOS comparator outputting one bit digital signal after comparing two analog input signals through alternately performing a track mode operation and latch mode operation decided by a clock signal having a constant period, including: a latching unit having the main/sub input terminal; a first switching transistor having the clock signal as a gate input and having one end coupled to main input terminal; a first load transistor diode-connected to the other end of the first switching transistor and a ground end; a second switching transistor having a gate receiving the clock signal as a gate input and one end coupled to the sub input terminal; and a second load transistor diode-connected to the second switching transistor and to the other end of the ground terminal.

Abstract: A switched-capacitor integrator eliminates noise caused by the switching of an input signal. For this purpose, the integrator includes a switched-capacitor unit for providing a capacitor with one of a first and a second input voltage in response to clock signals, a reference voltage providing unit for receiving a reference voltage and outputting an amplified reference voltage, a switching noise eliminating unit for maintaining an output of the reference voltage providing unit at a stabilized voltage level, an operational amplifying unit for receiving an output of the switched-capacitor unit as its negative input and the output of the reference voltage providing unit passed through the switching noise eliminating unit as its positive input and a feedback capacitor for feeding back an output of the operational amplifying unit to the negative input.

Abstract: The present invention provide an CMOS comparator outputting one bit digital signal after comparing two analog input signals through alternately performing a track mode operation and latch mode operation decided by a clock signal having a constant period, including: a latching unit having the main/sub input terminal; a first switching transistor having the clock signal as a gate input and having one end coupled to main input terminal; a first load transistor diode-connected to the other end of the first switching transistor and a ground end; a second switching transistor having a gate receiving the clock signal as a gate input and one end coupled to the sub input terminal; and a second load transistor diode-connected to the second switching transistor and to the other end of the ground terminal.

Abstract: A CMOS image sensor performing an analog correlated double sampling is disclosed. The CMOS image sensor may include an image capture device for capturing an image for analog image signal from an object an analog-to-digital converter for converting the analog image signal to a digital value using a ramp signal. In such an arrangement the analog-to-digital converter may includes a chopper-type comparator receiving the analog image signal and the ramp signal and a capacitor for receiving a start voltage of the ramp signal and charging a voltage level corresponding the start voltage of the ramp signal in a reset mode and for receiving a down-ramping signal of the ramp signal in a count mode in order to remove an device offset voltage. The analog-to-digital converter may also include a ramp signal generator providing the ramp signal to the analog-to-digital converter.

Abstract: A switched-capacitor integrator eliminates noise caused by the switching of an input signal. For this purpose, the integrator includes a switched-capacitor unit for providing a capacitor with one of a first and a second input voltage in response to clock signals, a reference voltage providing unit for receiving a reference voltage and outputting an amplified reference voltage, a switching noise eliminating unit for maintaining an output of the reference voltage providing unit at a stabilized voltage level, an operational amplifying unit for receiving an output of the switched-capacitor unit as its negative input and the output of the reference voltage providing unit passed through the switching noise eliminating unit as its positive input and a feedback capacitor for feeding back an output of the operational amplifying unit to the negative input.

Abstract: A CMOS image sensor performing an analog correlated double sampling is disclosed. The CMOS image sensor may include an image capture device for capturing an image for analog image signal from an object an analog-to-digital converter for converting the analog image signal to a digital value using a ramp signal. In such an arrangement the analog-to-digital converter may includes a chopper-type comparator receiving the analog image signal and the ramp signal and a capacitor for receiving a start voltage of the ramp signal and charging a voltage level corresponding the start voltage of the ramp signal in a reset mode and for receiving a down-ramping signal of the ramp signal in a count mode in order to remove an device offset voltage. The analog-to-digital converter may also include a ramp signal generator providing the ramp signal to the analog-to-digital converter.

Abstract: A CMOS image sensor performing an analog correlated double sampling is disclosed. The CMOS image sensor may include an image capture device for capturing an image for analog image signal from an object an analog-to-digital converter for converting the analog image signal to a digital value using a ramp signal. In such an arrangement the analog-to-digital converter may includes a chopper-type comparator receiving the analog image signal and the ramp signal and a capacitor for receiving a start voltage of the ramp signal and charging a voltage level corresponding the start voltage of the ramp signal in a reset mode and for receiving a down-ramping signal of the ramp signal in a count mode in order to remove an device offset voltage. The analog-to-digital converter may also include a ramp signal generator providing the ramp signal to the analog-to-digital converter.