Abstract: A base cell of a gate array architecture includes an increased number of transistors that can be interconnected or not interconnected so as to realize similar advantages as a having a library of transistors of different sizes. In one embodiment, each column a base cell contains two PMOS transistors and two NMOS transistors connected so as to share a single polysilicon (“poly”) gate electrode. Such an arrangement of the transistors in metal only programmable base cell architecture provides three different P and N transistor widths per poly gate and may provide nine different combinations transistor widths for P and N for design. The number of gate electrodes is minimized and their arrangement simplified such that the size of the base cell may be same size compared to traditional gate array base cell with four transistors. Moreover, only a single type of base cell need be provided, simplifying layout and design.