Abstract: Provided are a system for analyzing a mask topography, which can reduce calculation time and increase calculation accuracy in consideration of a mask topography effect, and a method of forming an image using the system. The system and method simultaneously obtains a first electric field using a Kirchhoff method without considering a pitch formed on a mask and obtains a second electric field using an electromagnetic field analysis method considering the pitch, and then determines a third electric field on a pupil surface of a projection lens by combining the first electric field and the second electric field of forming an image, so as to calculate the image of an optical lithography system which includes an illumination system and a projection optical system and to which the projection lens belongs.

Abstract: Provided are a system for analyzing a mask topography, which can reduce calculation time and increase calculation accuracy in consideration of a mask topography effect, and a method of forming an image using the system. The system and method simultaneously obtains a first electric field using a Kirchhoff method without considering a pitch formed on a mask and obtains a second electric field using an electromagnetic field analysis method considering the pitch, and then determines a third electric field on a pupil surface of a projection lens by combining the first electric field and the second electric field of forming an image, so as to calculate the image of an optical lithography system which includes an illumination system and a projection optical system and to which the projection lens belongs.

Abstract: A method of creating a layout of a set of masks including an alternating phase shifting mask (APSM) and a halftone phase shifting trim mask (HPSTM) is provided. The APSM includes first and second phase shifting areas and a first opaque pattern. The first and second phase shifting areas are disposed adjacent to each other and have different phases for generating destructive interference. Further, the first and second phase shifting areas define an access interconnection line. The first opaque pattern is formed on a transparent substrate to define the first and second phase shifting areas. The HPSTM includes a second opaque pattern on the transparent substrate and a halftone pattern. The second opaque pattern prevents an access interconnection line from being erased. The halftone pattern defines a pass interconnection line connected to the access interconnection line.

Abstract: A phase edge phase shift mask and a fabrication method thereof for enforcing a width of a field gate image located on a field region, which is weakened by a two exposure process, by using a phase shift mask and a trim mask on a semiconductor substrate, and enforcing a width of the field gate image to maximize a current driving capability of the semiconductor device.

Abstract: A set of masks including an alternating phase shifting mask (APSM) and a halftone phase shifting trim mask (HPSTM) is provided. The APSM includes first and second phase shifting areas and a first opaque pattern. The first and second phase shifting areas are disposed adjacent to each other and have different phases for generating destructive interference. Further, the first and second phase shifting areas define an access interconnection line. The first opaque pattern is formed on a transparent substrate to define the first and second phase shifting areas. The HPSTM includes a second opaque pattern on the transparent substrate and a halftone pattern. The second opaque pattern prevents an access interconnection line from being erased. The halftone pattern defines a pass interconnection line connected to the access interconnection line.

Abstract: A set of masks including an alternating phase shifting mask (APSM) and a halftone phase shifting trim mask (HPSTM) is provided. The APSM includes first and second phase shifting areas and a first opaque pattern. The first and second phase shifting areas are disposed adjacent to each other and have different phases for generating destructive interference. Further, the first and second phase shifting areas define an access interconnection line. The first opaque pattern is formed on a transparent substrate to define the first and second phase shifting areas. The HPSTM includes a second opaque pattern on the transparent substrate and a halftone pattern. The second opaque pattern prevents an access interconnection line from being erased. The halftone pattern defines a pass interconnection line connected to the access interconnection line.

Abstract: A phase edge phase shift mask and a fabrication method thereof for enforcing a width of a field gate image located on a field region, which is weakened by a two exposure process, by using a phase shift mask and a trim mask on a semiconductor substrate, and enforcing a width of the field gate image to maximize a current driving capability of the semiconductor device.

Abstract: A set of masks including an alternating phase shifting mask (APSM) and a halftone phase shifting trim mask (HPSTM) is provided. The APSM includes first and second phase shifting areas and a first opaque pattern. The first and second phase shifting areas are disposed adjacent to each other and have different phases for generating destructive interference. Further, the first and second phase shifting areas define an access interconnection line. The first opaque pattern is formed on a transparent substrate to define the first and second phase shifting areas. The HPSTM includes a second opaque pattern on the transparent substrate and a halftone pattern. The second opaque pattern prevents an access interconnection line from being erased. The halftone pattern defines a pass interconnection line connected to the access interconnection line.

Abstract: The present invention is to provide a method for forming ferroelectric films using a hot-wall chemical vapor deposition apparatus, comprising the steps of: heating the processing tube and a plurality of receptacles which contain ferroelectric source materials; loading wafers into said processing tube; conveying vaporized gases from said receptacles to a mixing chamber using carrier gas when said processing is set to a predetermined temperature and mixing said vaporized gases in said mixing chamber, by keeping said processing tube vacuum; providing said mixing chamber with oxidization gas and reaction speed control gas to control reaction speed in said processing tube; and injecting mixed gases in said mixing chamber into said processing tube through a gas injecting means and depositing said mixed gases in said mixing chamber on the wafers.

Abstract: An EEPROM including a selecting gate which overlaps with one side of a floating gate and a certain part of a source electrode and a control gate which overlaps with the other side of the floating gate and a certain part of a drain electrode, is improved in charge coupling ratio, showing an increase in program efficiency even at low outer voltages. Application of low outer voltages to the EEPROM brings about a decrease in both the breakdown voltage and the junction breakdown voltage of the gate oxide film of peripheral transistors, allowing a shallow junction and a thin gate oxide film process to be possible. A shallow junction can be effected by an ion-implanting process which results in formation of a source electrode and a drain electrode.