Patents by Inventor Soo-Ho Shin

Soo-Ho Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10380784
    Abstract: Provided herein is an electronic apparatus including a storage configured to store a texture image representing a characteristic of a particle of an object; and a processor configured to map the texture image to a plurality of locations where the particle exists and to generate a blending image by blending the mapped texture images, and to render the object based on the blending image.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: August 13, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-ho Shin, Soo-wan Park, Joon-seok Lee
  • Publication number: 20190194435
    Abstract: A polypropylene resin composition may include an amount of 40 to 60 wt % of a polypropylene resin, an amount of 1 to 10 wt % of a polyethylene resin, an amount of 10 to 20 wt % of an olefin elastomer, and an amount of 1 to 20 wt % of a reinforcing material wherein all the wt % are based on the total weight of the polypropylene resin composition. Accordingly, a high gloss may be obtained without a coating process and moldability of the polypropylene resin may be obtained. Further provided is a molded article of an interior material or an exterior material of a vehicle manufactured by using the polypropylene resin composition.
    Type: Application
    Filed: August 12, 2018
    Publication date: June 27, 2019
    Inventors: Kyeong Hoon Jang, Dae Sik Kim, Jaehyun An, Seul Yi, In Soo Han, Eun Seob Shin, Beom Ho Kim, Hyeok Lee
  • Patent number: 9966267
    Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 8, 2018
    Assignee: Samsung Electronics Co, Ltd.
    Inventors: Soo-ho Shin, Yong-sung Kim, Tae-young Chung
  • Publication number: 20170032969
    Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
    Type: Application
    Filed: October 13, 2016
    Publication date: February 2, 2017
    Inventors: Soo-ho SHIN, Yong-sung KIM, Tae-young CHUNG
  • Patent number: 9536868
    Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: January 3, 2017
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Keun-Nam Kim, Sun-Young Park, Soo-Ho Shin, Kye-Hee Yeom, Hyeon-Woo Jang, Jin-Won Jeong, Chang-Hyun Cho, Hyeong-Sun Hong
  • Patent number: 9496336
    Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 15, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-ho Shin, Yong-sung Kim, Tae-young Chung
  • Patent number: 9299827
    Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: March 29, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Soo Kim, Soo-Ho Shin, Ho-In Ryu, Hyeong-Sun Hong
  • Publication number: 20160035714
    Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.
    Type: Application
    Filed: October 5, 2015
    Publication date: February 4, 2016
    Inventors: KEUN-NAM KIM, SUN-YOUNG PARK, SOO-HO SHIN, KYE-HEE YEOM, HYEON-WOO JANG, JIN-WON JEONG, CHANG-HYUN CHO, HYEONG-SUN HONG
  • Publication number: 20150318350
    Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
    Type: Application
    Filed: June 25, 2015
    Publication date: November 5, 2015
    Inventors: Soo-ho Shin, Yong-sung Kim, Tae-young Chung
  • Patent number: 9177891
    Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: November 3, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keun-Nam Kim, Sun-Young Park, Soo-Ho Shin, Kye-Hee Yeom, Hyeon-Woo Jang, Jin-Won Jeong, Chang-Hyun Cho, Hyeong-Sun Hong
  • Patent number: 9099325
    Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: August 4, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sung Kim, Tae-Young Chung, Soo-Ho Shin
  • Publication number: 20150035025
    Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Inventors: Bong-Soo KIM, Soo-Ho SHIN, Ho-In RYU, Hyeong-Sun HONG
  • Patent number: 8872262
    Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Soo Kim, Hyeong-Sun Hong, Soo-Ho Shin, Ho-In Ryu
  • Patent number: 8873277
    Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Soo-ho Shin, Won-woo Lee, Jeong-soo Park, Young-yong Byun, Seong-jin Jang, Sang-woong Shin
  • Publication number: 20140110851
    Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 24, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keun-Nam KIM, Sun-Young PARK, Soo-Ho SHIN, Kye-Hee YEOM, Hyeon-Woo JANG, Jin-Won JEONG, Chang-Hyun CHO, Hyeong-sun HONG
  • Publication number: 20140103482
    Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
    Type: Application
    Filed: December 17, 2013
    Publication date: April 17, 2014
    Inventors: Yong-Sung Kim, Tae-Young CHUNG, Soo-Ho SHIN
  • Patent number: 8648423
    Abstract: Provided is a semiconductor device in which a short margin between a storage contact plug and a bit line contact plug may be increased. The device includes a substrate including isolation regions and active regions defined by the isolation regions, gates disposed in the substrate and configured to intersect the active regions and define source regions and drain regions in the active regions, an interlayer insulating layer disposed on the substrate, bit line contact plugs configured to penetrate the interlayer insulating layer and contact the drain regions, and first bit line structures and second bit line structures disposed on the interlayer insulating layer. The first bit line structures include first bit line conductive patterns and first bit line spacers covering sidewalls of the first bit line conductive patterns.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: February 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hee Han, Soo-Ho Shin
  • Patent number: 8637934
    Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sung Kim, Tae-Young Chung, Soo-Ho Shin
  • Patent number: 8563373
    Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: October 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sung Kim, Tae-Young Chung, Soo-Ho Shin
  • Publication number: 20130248984
    Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
    Type: Application
    Filed: May 22, 2013
    Publication date: September 26, 2013
    Inventors: Yong-Sung Kim, Tae-Young Chung, Soo-Ho Shin