Patents by Inventor Soo-Ho Shin
Soo-Ho Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240057323Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device includes a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.Type: ApplicationFiled: October 23, 2023Publication date: February 15, 2024Inventors: Hyeon Woo JANG, Soo Ho SHIN, Dong Sik PARK, Jong Min LEE, Ji Hoon CHANG
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Patent number: 11832442Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device comprises a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.Type: GrantFiled: October 4, 2021Date of Patent: November 28, 2023Inventors: Hyeon Woo Jang, Soo Ho Shin, Dong Sik Park, Jong Min Lee, Ji Hoon Chang
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Publication number: 20230189504Abstract: A semiconductor memory device includes a landing pad on a substrate, a lower electrode on and connected to the landing pad, a dielectric layer on and extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode, the upper plate electrode including a first sub-plate electrode and a second sub-plate electrode doped with boron, a first concentration of the boron in the first sub-plate electrode being greater than a second concentration of the boron in the second sub-plate electrode.Type: ApplicationFiled: September 27, 2022Publication date: June 15, 2023Inventors: Keon Hee PARK, Soo Ho SHIN, Hyeon-Woo JANG, Dong-Sik PARK, Ga Eun LEE
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Publication number: 20220262803Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device comprises a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.Type: ApplicationFiled: October 4, 2021Publication date: August 18, 2022Inventors: Hyeon Woo JANG, Soo Ho SHIN, Dong Sik PARK, Jong Min LEE, Ji Hoon CHANG
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Publication number: 20220189966Abstract: A semiconductor memory device comprises a substrate which includes a cell region, and a peri region defined around the cell region, the cell region including an active region defined by an element separation film, a storage pad connected to the active region of the cell region, a peri gate structure placed on the substrate of the peri region, a peri contact plug placed on both sides of the peri gate structure and connected to the substrate, a first interlayer insulating film which is placed on the storage pad and the pen contact plug, and includes a nitride-based insulating material, and an information storage unit connected to the storage pad, wherein a thickness of the first interlayer insulating film on an upper surface of the storage pad is smaller than a thickness of the first interlayer insulating film on an upper surface of the peri contact plug.Type: ApplicationFiled: July 6, 2021Publication date: June 16, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Hyeon-Woo JANG, Soo Ho SHIN
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Patent number: 9966267Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.Type: GrantFiled: October 13, 2016Date of Patent: May 8, 2018Assignee: Samsung Electronics Co, Ltd.Inventors: Soo-ho Shin, Yong-sung Kim, Tae-young Chung
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Publication number: 20170032969Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.Type: ApplicationFiled: October 13, 2016Publication date: February 2, 2017Inventors: Soo-ho SHIN, Yong-sung KIM, Tae-young CHUNG
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Patent number: 9536868Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.Type: GrantFiled: October 5, 2015Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO, LTD.Inventors: Keun-Nam Kim, Sun-Young Park, Soo-Ho Shin, Kye-Hee Yeom, Hyeon-Woo Jang, Jin-Won Jeong, Chang-Hyun Cho, Hyeong-Sun Hong
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Patent number: 9496336Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.Type: GrantFiled: June 25, 2015Date of Patent: November 15, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-ho Shin, Yong-sung Kim, Tae-young Chung
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Patent number: 9299827Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.Type: GrantFiled: October 16, 2014Date of Patent: March 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-Soo Kim, Soo-Ho Shin, Ho-In Ryu, Hyeong-Sun Hong
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Publication number: 20160035714Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.Type: ApplicationFiled: October 5, 2015Publication date: February 4, 2016Inventors: KEUN-NAM KIM, SUN-YOUNG PARK, SOO-HO SHIN, KYE-HEE YEOM, HYEON-WOO JANG, JIN-WON JEONG, CHANG-HYUN CHO, HYEONG-SUN HONG
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Publication number: 20150318350Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.Type: ApplicationFiled: June 25, 2015Publication date: November 5, 2015Inventors: Soo-ho Shin, Yong-sung Kim, Tae-young Chung
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Patent number: 9177891Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.Type: GrantFiled: October 3, 2013Date of Patent: November 3, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Keun-Nam Kim, Sun-Young Park, Soo-Ho Shin, Kye-Hee Yeom, Hyeon-Woo Jang, Jin-Won Jeong, Chang-Hyun Cho, Hyeong-Sun Hong
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Patent number: 9099325Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.Type: GrantFiled: December 17, 2013Date of Patent: August 4, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Sung Kim, Tae-Young Chung, Soo-Ho Shin
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Publication number: 20150035025Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.Type: ApplicationFiled: October 16, 2014Publication date: February 5, 2015Inventors: Bong-Soo KIM, Soo-Ho SHIN, Ho-In RYU, Hyeong-Sun HONG
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Patent number: 8873277Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.Type: GrantFiled: October 10, 2012Date of Patent: October 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeoung-won Seo, Soo-ho Shin, Won-woo Lee, Jeong-soo Park, Young-yong Byun, Seong-jin Jang, Sang-woong Shin
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Patent number: 8872262Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.Type: GrantFiled: May 18, 2010Date of Patent: October 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-Soo Kim, Hyeong-Sun Hong, Soo-Ho Shin, Ho-In Ryu
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Publication number: 20140110851Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.Type: ApplicationFiled: October 3, 2013Publication date: April 24, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Keun-Nam KIM, Sun-Young PARK, Soo-Ho SHIN, Kye-Hee YEOM, Hyeon-Woo JANG, Jin-Won JEONG, Chang-Hyun CHO, Hyeong-sun HONG
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Publication number: 20140103482Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.Type: ApplicationFiled: December 17, 2013Publication date: April 17, 2014Inventors: Yong-Sung Kim, Tae-Young CHUNG, Soo-Ho SHIN
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Patent number: 8648423Abstract: Provided is a semiconductor device in which a short margin between a storage contact plug and a bit line contact plug may be increased. The device includes a substrate including isolation regions and active regions defined by the isolation regions, gates disposed in the substrate and configured to intersect the active regions and define source regions and drain regions in the active regions, an interlayer insulating layer disposed on the substrate, bit line contact plugs configured to penetrate the interlayer insulating layer and contact the drain regions, and first bit line structures and second bit line structures disposed on the interlayer insulating layer. The first bit line structures include first bit line conductive patterns and first bit line spacers covering sidewalls of the first bit line conductive patterns.Type: GrantFiled: September 22, 2011Date of Patent: February 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hee Han, Soo-Ho Shin