Abstract: A memory system includes a controller configured to transmit a reset write command and reset write data, and transmit a set write command and set write data; and at least one memory device configured to generate seed data by performing a first operation on the reset write data and read data read out from a target memory area in response to the reset write command, generate write data by performing a second operation on the seed data and the set write data in response to the set write command, and write back the write data to the target memory area.

Abstract: A string filter device may include an input buffer group and a string comparator group. The input buffer group may store a plurality of string group data segments. Each of the plurality of string group data segments has a first size and includes a plurality of string data having a variable size. The string comparator group may extract a plurality of different sub-string group data segments having a second size among the plurality of string group data segments, and compare, in parallel, each of the plurality of sub-string group data segments with query data, using a plurality of string comparators.

Abstract: A memory system includes a controller configured to transmit a reset write command and reset write data, and transmit a set write command and set write data; and at least one memory device configured to generate seed data by performing a first operation on the reset write data and read data read out from a target memory area in response to the reset write command, generate write data by performing a second operation on the seed data and the set write data in response to the set write command, and write back the write data to the target memory area.

Abstract: A memory system for efficiently processing data in performing a job may include a plurality of memory devices configured to store data, a main data processor configured to access the plurality of memory devices, a sub data processor group including a plurality of sub data processors each configured to access the plurality of memory devices, respectively, a host interface configured to receive, from a host, a request for a job, and a job controller configured to perform the job by using one of the main data processor and the sub data processor group depending on whether accesses to the plurality of memory devices are related to each other for the job.

Abstract: A data processing system includes at least one pooled memory node, at least one processing node, and a switch node coupled to the at least one pooled memory node and the at least one processing node. The data processing system also includes a master node configured to transmit task information to a first processing node among the at least one processing node through the switch node and configured to transmit a memory address range of a first pooled memory node among the at least one pooled memory node to the switch node. The switch node processes a first memory access request transmitted by the first processing node based on the task information, for the first pooled memory node, based on the memory address range.

Abstract: A data processing system may include a plurality of memory modules, a controller, a power supply and a plurality of switches. Each of the memory modules may include a plurality of pages. The controller may control operations of the memory modules. The power supply may provide the memory modules with a power. The switches may be arranged corresponding to each of the memory modules. The switches may be selectively driven in response to a switch drive signal from the controller.

Abstract: A data processing system includes at least one pooled memory node, at least one processing node, and a switch node coupled to the at least one pooled memory node and the at least one processing node. The data processing system also includes a master node configured to transmit task information to a first processing node among the at least one processing node through the switch node and configured to transmit a memory address range of a first pooled memory node among the at least one pooled memory node to the switch node. The switch node processes a first memory access request transmitted by the first processing node based on the task information, for the first pooled memory node, based on the memory address range.

Abstract: A data processing system may include a plurality of memory modules, a controller, a power supply and a plurality of switches. Each of the memory modules may include a plurality of pages. The controller may control operations of the memory modules. The power supply may provide the memory modules with a power. The switches may be arranged corresponding to each of the memory modules. The switches may be selectively driven in response to a switch drive signal from the controller.

Abstract: A controller that controls a nonvolatile memory apparatus may include a first memory configured to temporarily store user data, a second memory including a plurality of memory regions composed of one or more meta regions for storing meta data and at least one spare region, and a processor configured to control the first memory and the second memory and perform first start-gap wear leveling on at least one meta region using the at least one spare region as a gap.

Abstract: A data processing apparatus may include a master device, a slave device, and a controller configured to arbitrate communication between the master device and the slave device by: setting a respective Time-out Counter (TC) for each of requests transmitted from the master device, allocating one or more virtual channels to each of one or more request groups, the one or more virtual channels respectively corresponding to priority levels, associating a request with a virtual channel corresponding to the priority level of the request, for each request group, selecting one of the leading requests of the respective virtual channels according to the TCs and transmitting the selected request to the slave device.

Abstract: A data processing system may include a plurality of memory modules, a controller, a power supply and a plurality of switches. Each of the memory modules may include a plurality of pages. The controller may control operations of the memory modules. The power supply may provide the memory modules with a power. The switches may be arranged corresponding to each of the memory modules. The switches may be selectively driven in response to a switch drive signal from the controller.

Abstract: A data processing system includes at least one pooled memory node, at least one processing node, and a switch node coupled to the at least one pooled memory node and the at least one processing node. The data processing system also includes a master node configured to transmit task information to a first processing node among the at least one processing node through the switch node and configured to transmit a memory address range of a first pooled memory node among the at least one pooled memory node to the switch node. The switch node processes a first memory access request transmitted by the first processing node based on the task information, for the first pooled memory node, based on the memory address range.

Abstract: A data processing system includes at least one pooled memory node, at least one processing node, and a switch node coupled to the at least one pooled memory node and the at least one processing node. The data processing system also includes a master node configured to transmit task information to a first processing node among the at least one processing node through the switch node and configured to transmit a memory address range of a first pooled memory node among the at least one pooled memory node to the switch node. The switch node processes a first memory access request transmitted by the first processing node based on the task information, for the first pooled memory node, based on the memory address range.

Abstract: A data processing system includes at least one pooled memory node, at least one processing node, and a switch node coupled to the at least one pooled memory node and the at least one processing node. The data processing system also includes a master node configured to transmit task information to a first processing node among the at least one processing node through the switch node and configured to transmit a memory address range of a first pooled memory node among the at least one pooled memory node to the switch node. The switch node processes a first memory access request transmitted by the first processing node based on the task information, for the first pooled memory node, based on the memory address range.

Abstract: A data processing apparatus may include a master device, a slave device, and a controller configured to arbitrate communication between the master device and the slave device by: setting a respective Time-out Counter (TC) for each of requests transmitted from the master device, allocating one or more virtual channels to each of one or more request groups, the one or more virtual channels respectively corresponding to priority levels, associating a request with a virtual channel corresponding to the priority level of the request, for each request group, selecting one of the leading requests of the respective virtual channels according to the TCs and transmitting the selected request to the slave device.

Abstract: A controller that controls a nonvolatile memory apparatus may include a first memory configured to temporarily store user data, a second memory including a plurality of memory regions composed of one or more meta regions for storing meta data and at least one spare region, and a processor configured to control the first memory and the second memory and perform first start-gap wear leveling on at least one meta region using the at least one spare region as a gap.

Abstract: A data processing system may include a plurality of memory modules, a controller, a power supply and a plurality of switches. Each of the memory modules may include a plurality of pages. The controller may control operations of the memory modules. The power supply may provide the memory modules with a power. The switches may be arranged corresponding to each of the memory modules. The switches may be selectively driven in response to a switch drive signal from the controller.

Abstract: A data processing system includes at least one pooled memory node, at least one processing node, and a switch node coupled to the at least one pooled memory node and the at least one processing node. The data processing system also includes a master node configured to transmit task information to a first processing node among the at least one processing node through the switch node and configured to transmit a memory address range of a first pooled memory node among the at least one pooled memory node to the to switch node. The switch node processes a first memory access request transmitted by the first processing node based on the task information, for the first pooled memory node, based on the memory address range.

Abstract: A data storage device includes a nonvolatile memory device including a memory region, the memory region including a plurality of memory units; and a controller suitable for monitoring an elapsed time and a write count of the memory region, and performing a wear leveling operation for at least one memory unit selected among the plurality of memory units depending on a monitoring result.

Abstract: A data storage device includes a nonvolatile memory device including a reference memory region and a normal memory region, and suitable for determining whether to perform a refresh operation, based on the reference memory region; and a controller suitable for determining a first memory region in the normal memory region based on wear leveling operation data, and controlling the nonvolatile memory device to perform the refresh operation for a second memory region excluding the first memory region in the normal memory region.