Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line elongated in one direction, a data line crossing over the gate line, a thin film transistor near a crossing point of the gate and data lines and connected to the gate and data lines, an independent portion under the data line at the crossing point, the portion being separated from the gate line, and a pixel electrode connected to the thin film transistor. The independent portion may be inside the gate line. The parasitic capacitor between the gate line and the data line can be reduced and the amount of light from the backlight device can be reduced.

Abstract: A gate driving circuit for a liquid crystal display device includes a plurality of shift register stages each including pull-up and pull-down transistors, wherein each of the pull-up and pull-down transistors is connected to a gate driving signal output terminal and controlled by voltages on first and second nodes, respectively, and wherein the pull-down transistors of a (2n?1)th shift register stage and a (2n)th shift register stage are connected to each other; and a control signal generating unit alternately supplying one of first and second control signals to the pull-down transistors of the (2n?1)th and (2n)th shift register stages and supplying the other of the first and second control signals to the pull-down transistors of the (2n+1)th and (2n+2)th shift register stages, wherein n is an positive integer.

Abstract: A driving circuit for a flat panel display device includes shift register stages, each containing: a first TFT charging a Q node according to a start signal; a second TFT discharging the Q node according to an output voltage of a next shift register stage; a pull-up unit increasing an output voltage according to the Q node voltage; an odd pull-down unit decreasing the output voltage in an odd frame according to a QB-o node voltage; and an even pull-down unit decreasing the output voltage in an even frame according to a QB-e node voltage. A gate and drain of a third odd TFT connected to the QB-o node are connected to each other and receive an odd source voltage. A gate and drain of the third even TFT connected to the QB-e node are connected to each other and receive an even source voltage.

Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line elongated in one direction, a data line crossing over the gate line, a thin film transistor near a crossing point of the gate and data lines and connected to the gate and data lines, an independent portion under the data line at the crossing point, the portion being separated from the gate line, and a pixel electrode connected to the thin film transistor. The independent portion may be inside the gate line. The parasitic capacitor between the gate line and the data line can be reduced. And amount of light from the backlight device can be reduced.

Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line elongated in one direction, a data line crossing over the gate line, a thin film transistor near a crossing point of the gate and data lines and connected to the gate and data lines, an independent portion under the data line at the crossing point, the portion being separated from the gate line, and a pixel electrode connected to the thin film transistor. The independent portion may be inside the gate line. The parasitic capacitor between the gate line and the data line can be reduced. And amount of light from the backlight device can be reduced.

Abstract: A gate driving circuit for a liquid crystal display device includes a plurality of shift register stages each including pull-up and pull-down transistors, wherein each of the pull-up and pull-down transistors is connected to a gate driving signal output terminal and controlled by voltages on first and second nodes, respectively, and wherein the pull-down transistors of a (2n?1)th shift register stage and a (2n)th shift register stage are connected to each other; and a control signal generating unit alternately supplying one of first and second control signals to the pull-down transistors of the (2n?1)th and (2n)th shift register stages and supplying the other of the first and second control signals to the pull-down transistors of the (2n+1)th and (2n+2)th shift register stages, wherein n is an positive integer.

Abstract: A driving circuit for a flat panel display device includes shift register stages, each containing: a first TFT charging a Q node according to a start signal; a second TFT discharging the Q node according to an output voltage of a next shift register stage; a pull-up unit increasing an output voltage according to the Q node voltage; an odd pull-down unit decreasing the output voltage in an odd frame according to a QB-o node voltage; and an even pull-down unit decreasing the output voltage in an even frame according to a QB-e node voltage. A gate and drain of a third odd TFT connected to the QB-o node are connected to each other and receive an odd source voltage. A gate and drain of the third even TFT connected to the QB-e node are connected to each other and receive an even source voltage.

Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line elongated in one direction, a data line crossing over the gate line, a thin film transistor near a crossing point of the gate and data lines and connected to the gate and data lines, an independent portion under the data line at the crossing point, the portion being separated from the gate line, and a pixel electrode connected to the thin film transistor. The independent portion may be inside the gate line.