Abstract: Provided is a full-duplex NOMA-based transmit power control device, the device including a state information collector configured to set a role of each of vehicle user equipments (VUEs) constituting a sub-system in a hyper-fractionated zone of a Manhattan mobility model and collect network state information from the sub-system, an actor network configured to determine transmit power of each of the VUEs on the basis of the network state information, a reward calculator configured to calculate a reward value for the network state information and the transmit power, a replay memory configured to store the network state information collected by the network state information collector, the transmit power determined by the actor network, and the reward value calculated by the reward calculator, and a critic network configured to evaluate the transmit power determined by the actor network and give feedback to the actor network.

Abstract: A memory storage device that performs real-time monitoring is provided. The memory storage device comprises a memory controller, and a status indicating module/circuit, wherein the memory controller is configured to perform a first a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which a second initialization operation is performed. The status indicating circuit includes a first transistor configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor.

Abstract: The disclosure generally relates to techniques for efficiently allocating resources allocated from a macro base station by estimating the communication possibility of each sensor without direct communication with the sensor in a mobile base station. A method for resource allocation in a mobile base station may include detecting at least one sensor within a communicable range of the mobile base station, estimating a communication possibility of the sensor based on a message queue and a remaining battery level of the at least one sensor, receiving resource allocation from a macro base station based on the communication possibility, and allocating the allocated resource to the sensor.

Abstract: A memory storage device that performs real-time monitoring is provided. The memory storage device comprises a memory controller, and a status indicating module/circuit, wherein the memory controller is configured to perform a first a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which a second initialization operation is performed. The status indicating circuit includes a first transistor configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor.

Abstract: The disclosure generally relates to techniques for efficiently allocating resources allocated from a macro base station by estimating the communication possibility of each sensor without direct communication with the sensor in a mobile base station. A method for resource allocation in a mobile base station may include detecting at least one sensor within a communicable range of the mobile base station, estimating a communication possibility of the sensor based on a message queue and a remaining battery level of the at least one sensor, receiving resource allocation from a macro base station based on the communication possibility, and allocating the allocated resource to the sensor.

Abstract: Provided is a vote authentication server. The vote authentication server includes a communication unit configured to receive a vote authority authentication request information transmitted from a voter terminal; a vote token management unit configured to issue a vote token according to vote authority authentication, provide the vote token to the voter terminal, and receive the vote token from the voter terminal when a voting is completed; a vote token identification unit configured to assign an identification code to the issued vote token and store the identification code of the issued vote token; and a block chain unit configured to create a block of an authentication block chain network using the vote token provided from the voter terminal and the vote token provided to the voter terminal.

Abstract: A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of cell cores which include a first cell core corresponding to a first channel that is a normal channel and a second cell core corresponding to a second channel that is a failed channel; and an access circuit configured to perform address remapping by converting a first address of at least a first failed cell in the first cell core into a second address of at least a second cell in the second cell core, and to transmit data of at least the second cell through the first channel.

Abstract: A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of cell cores which include a first cell core corresponding to a first channel that is a normal channel and a second cell core corresponding to a second channel that is a failed channel; and an access circuit configured to perform address remapping by converting a first address of at least a first failed cell in the first cell core into a second address of at least a second cell in the second cell core, and to transmit data of at least the second cell through the first channel.