Abstract: A lower module of a power electronic device includes a lower module included in a power electronic device that is divided into an upper module and a lower module by an intermediate plate and comprises a blower fan to introduce air into the inner space of the lower module; a plurality of capacitors installed in a suspended form on the intermediate plate and spaced apart from the blower fan; a heat sink having a plurality of heat dissipation fins through which heat generated from a heating component disposed on the upper module is conducted, and disposed adjacent to the capacitors to cool the plurality of heat dissipation fins by air moved from the plurality of capacitors; a DC reactor cooled by the air moved from the heat dissipation fins; and a discharge plate having a vent hole to discharge the air moved from the DC reactor to the outside.

Abstract: A memory storage device that performs real-time monitoring is provided. The memory storage device comprises a memory controller, and a status indicating module/circuit, wherein the memory controller is configured to perform a first a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which a second initialization operation is performed. The status indicating circuit includes a first transistor configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor.

Abstract: Disclosed is a battery cell, which includes a battery case having an accommodation portion in which an electrode assembly is mounted, and a sealing portion formed by sealing an outer periphery thereof; an electrode lead electrically connected to an electrode tab included in the electrode assembly and protruding out of the battery case via the sealing portion; and a lead film located at a portion corresponding to the sealing portion in at least one of an upper portion and a lower portion of the electrode lead, wherein a gas discharge guiding unit is inserted in the lead film, the battery case includes a cover portion extending from the sealing portion, and the cover portion is located on the lead film and protrudes in an outer direction of the battery case.

Abstract: The present disclosure relates to a secondary battery comprising an electrode assembly having an electrode lead attached thereto, a case comprising a receiving portion in which the electrode assembly is received and a sealing portion comprising a sealant resin and configured to seal the electrode assembly, a lead film configured to cover a portion of an outer surface of the electrode lead and interposed between the electrode lead and the case, a vent area disposed in at least a portion of the case, and a vent member comprising a first layer comprising a resin having lower melting point than the sealant resin, and a second layer disposed on at least one surface of the first layer and comprising an adhesive material. The vent member may be inserted into the vent area. A thickness of the second layer may be equal to or smaller than 5 ?m.

Abstract: The disclosure generally relates to techniques for efficiently allocating resources allocated from a macro base station by estimating the communication possibility of each sensor without direct communication with the sensor in a mobile base station. A method for resource allocation in a mobile base station may include detecting at least one sensor within a communicable range of the mobile base station, estimating a communication possibility of the sensor based on a message queue and a remaining battery level of the at least one sensor, receiving resource allocation from a macro base station based on the communication possibility, and allocating the allocated resource to the sensor.

Abstract: A memory storage device that performs real-time monitoring is provided. The memory storage device comprises a memory controller, and a status indicating module/circuit, wherein the memory controller is configured to perform a first a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which a second initialization operation is performed. The status indicating circuit includes a first transistor configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor.

Abstract: The disclosure generally relates to techniques for efficiently allocating resources allocated from a macro base station by estimating the communication possibility of each sensor without direct communication with the sensor in a mobile base station. A method for resource allocation in a mobile base station may include detecting at least one sensor within a communicable range of the mobile base station, estimating a communication possibility of the sensor based on a message queue and a remaining battery level of the at least one sensor, receiving resource allocation from a macro base station based on the communication possibility, and allocating the allocated resource to the sensor.

Abstract: Provided is a vote authentication server. The vote authentication server includes a communication unit configured to receive a vote authority authentication request information transmitted from a voter terminal; a vote token management unit configured to issue a vote token according to vote authority authentication, provide the vote token to the voter terminal, and receive the vote token from the voter terminal when a voting is completed; a vote token identification unit configured to assign an identification code to the issued vote token and store the identification code of the issued vote token; and a block chain unit configured to create a block of an authentication block chain network using the vote token provided from the voter terminal and the vote token provided to the voter terminal.

Abstract: A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of cell cores which include a first cell core corresponding to a first channel that is a normal channel and a second cell core corresponding to a second channel that is a failed channel; and an access circuit configured to perform address remapping by converting a first address of at least a first failed cell in the first cell core into a second address of at least a second cell in the second cell core, and to transmit data of at least the second cell through the first channel.

Abstract: A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of cell cores which include a first cell core corresponding to a first channel that is a normal channel and a second cell core corresponding to a second channel that is a failed channel; and an access circuit configured to perform address remapping by converting a first address of at least a first failed cell in the first cell core into a second address of at least a second cell in the second cell core, and to transmit data of at least the second cell through the first channel.