Abstract: An output buffer circuit includes an amplifier and a transmission circuit. The amplifier includes a plurality of inputs and an output. The inputs provide first input signals and second input signals to the amplifier. The output provides an output signal as a first input signal of the first input signals to the amplifier. The transmission circuit has an input coupled to the output of the amplifier and further has an output that provides a transmission circuit output signal as a second input signal of the second input signals to the amplifier.

Abstract: An amplifier for an output buffer includes an operational amplifier including a first input terminal, a second input terminal, and an output terminal, the operational amplifier is configured to generate an input bias current and amplify a voltage difference between signals applied to the first input terminal and the second input terminal, and to output the amplified voltage difference; and a self-bias circuit connected to the first input terminal and the second input terminal, the self-bias circuit is configured to generate first and second current paths when the voltage difference is equal to or greater than a predetermined voltage, to generate a tail current on the first or second current path, and to add the generated tail current to the input bias current of the operational amplifier, wherein the second input terminal is connected to the output terminal.

Abstract: Embodiments may disclose a power on reset circuit, which includes: a current mirror connected to a power node, the power node receiving a variable power supply voltage, the current mirror being configured to supply a first current to a first line and a second current to a second line; a comparative voltage generator configured to generate a comparative voltage using the first current provided via the first line; a driver connected to the second line, the driver being configured to activate a reset signal in response to a voltage of the second line; and a ground selecting transistor configured to connect the second line and a ground node according to the comparative voltage.

Abstract: An output buffer circuit includes an amplifier and a transmission circuit. The amplifier includes a plurality of inputs and an output. The inputs provide first input signals and second input signals to the amplifier. The output provides an output signal as a first input signal of the first input signals to the amplifier. The transmission circuit has an input coupled to the output of the amplifier and further has an output that provides a transmission circuit output signal as a second input signal of the second input signals to the amplifier.

Abstract: A method of generating a driving voltage includes inputting a test gradation voltage to a first input terminal and a second input terminal of a buffer, latching the logic level of a test driving voltage output from an output terminal of the buffer, setting the buffer to a first type when the logic level of the test driving voltage is high level and setting the buffer to a second type when the logic level of the test driving voltage is low level, and operating the buffer set to the first type or the second type to generate a driving voltage corresponding to a gradation voltage.

Abstract: An amplifier for an output buffer includes an operational amplifier including a first input terminal, a second input terminal, and an output terminal, the operational amplifier is configured to generate an input bias current and amplify a voltage difference between signals applied to the first input terminal and the second input terminal, and to output the amplified voltage difference; and a self-bias circuit connected to the first input terminal and the second input terminal, the self-bias circuit is configured to generate first and second current paths when the voltage difference is equal to or greater than a predetermined voltage, to generate a tail current on the first or second current path, and to add the generated tail current to the input bias current of the operational amplifier, wherein the second input terminal is connected to the output terminal.

Abstract: Embodiments may disclose a power on reset circuit, which includes: a current mirror connected to a power node, the power node receiving a variable power supply voltage, the current mirror being configured to supply a first current to a first line and a second current to a second line; a comparative voltage generator configured to generate a comparative voltage using the first current provided via the first line; a driver connected to the second line, the driver being configured to activate a reset signal in response to a voltage of the second line; and a ground selecting transistor configured to connect the second line and a ground node according to the comparative voltage.

Abstract: A display device includes a source driver. The source driver includes a power supply and a gamma voltage output unit. The power supply generates a power supply voltage and a plurality of reference voltages. The power supply voltage is stabilized in a power-up operating mode. The plurality of reference voltages are stabilized after a stabilization time period has elapsed in the power-up operating mode. The gamma voltage output unit generates a plurality of gamma voltages using the power supply voltage for the stabilization time period in the power-up operating mode, and generates the plurality of gamma voltages using the plurality of reference voltages after the stabilization time period has elapsed.

Abstract: A method of generating a driving voltage includes inputting a test gradation voltage to a first input terminal and a second input terminal of a buffer, latching the logic level of a test driving voltage output from an output terminal of the buffer, setting the buffer to a first type when the logic level of the test driving voltage is high level and setting the buffer to a second type when the logic level of the test driving voltage is low level, and operating the buffer set to the first type or the second type to generate a driving voltage corresponding to a gradation voltage.