Abstract: A semiconductor package provided. The semiconductor package includes an interposer layer including a first surface and a second surface opposing each other, a first semiconductor chip and a second semiconductor chip on the first surface of the interposer layer, and a block copolymer film on the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chip are different from each other. The block copolymer film includes a first pattern and a second pattern, which are different from each other, and one of the first pattern and the second pattern contains graphite.

Abstract: A semiconductor package provided. The semiconductor package includes an interposer layer including a first surface and a second surface opposing each other, a first semiconductor chip and a second semiconductor chip on the first surface of the interposer layer, and a block copolymer film on the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chip are different from each other. The block copolymer film includes a first pattern and a second pattern, which are different from each other, and one of the first pattern and the second pattern contains graphite.

Abstract: A semiconductor device includes a substrate, a protection layer on the substrate that includes a trench that penetrates therethrough, a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer; and an upper bump on the lower bump. The protection layer includes a first part that surrounds the trench and a second part that surrounds the first part. A first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer.

Abstract: A semiconductor package includes a mounting substrate having a chip-mounting region and a peripheral region. A first semiconductor chip is mounted on the chip-mounting region of the mounting substrate. A first molding member covers at least a portion of the first semiconductor chip on the mounting substrate. A plurality of first conductive connection members penetrate through at least a portion of the first molding member to protrude from the first molding member. The first conductive connection members are electrically connected to a plurality of ground connection pads provided on the peripheral region of the mounting substrate, respectively. An electromagnetic interference (EMI) shield member is disposed on an upper surface of the first molding member to cover the first semiconductor chip. The EMI shield member is supported by the first conductive molding members and spaced apart from the first molding member.

Abstract: A semiconductor package includes a mounting substrate having a chip-mounting region and a peripheral region, a first semiconductor chip mounted on the chip-mounting region of the mounting substrate, a first molding member on the mounting substrate to cover at least a portion of the first semiconductor chip, a plurality of first conductive connection members penetrating at least a portion of the first molding member, the first conductive connection members electrically connected to a plurality of ground connection pads provided on the peripheral region of the mounting substrate, respectively, and an electromagnetic interference (EMI) shield member covering the first semiconductor chip and including a graphite layer electrically connected to the first conductive connection members.

Abstract: A multi-layer printed circuit board (PCB) and a method for fabricating the same are provided. The multi-layer printed circuit board may include a first film and a first insulation layer. The first film may include a first via therein and the first film may further include a first conductive pattern on an upper surface thereof and the first conductive layer may be electrically connected to the first via. The first insulation layer may be on the upper surface of the first film and the first insulation layer may include a second via therein and a second conductive pattern on an upper surface thereof and the second conductive pattern may be electrically connected to the second via. The second via may be electrically connected to the first conductive pattern.

Abstract: A multi-layer printed circuit board (PCB) and a method for fabricating the same are provided. The multi-layer printed circuit board may include a first film and a first insulation layer. The first film may include a first via therein and the first film may further include a first conductive pattern on an upper surface thereof and the first conductive layer may be electrically connected to the first via. The first insulation layer may be on the upper surface of the first film and the first insulation layer may include a second via therein and a second conductive pattern on an upper surface thereof and the second conductive pattern may be electrically connected to the second via. The second via may be electrically connected to the first conductive pattern.