Abstract: A secondary battery includes an electrode assembly including a positive electrode plate, a negative electrode plate, and a separator disposed between the positive electrode plate and the negative electrode plate, wherein the electrode assembly has a first end, a second end opposite the first end, a first side and a second side opposite the first side, a pouch configured to surround the electrode assembly, and an inner support installed between the pouch and the electrode assembly to support the inside of the pouch.

Abstract: Operating a selector device that controls access of a signal to a memory element may comprise applying a main operating voltage pulse and a refresh voltage pulse to the selector device. The refresh voltage pulse and main operating voltage pulse have opposite polarities. A magnitude of the main operating voltage pulse is greater than or equal to a threshold voltage for turning on the selector device, and a maximum magnitude of the refresh voltage pulse is less than the threshold voltage. The refresh voltage pulse reduces a difference between the threshold voltage and a turn-off voltage of the selector device, and may be applied immediately before or immediately after the main operating voltage pulse. An electronic circuit may include the selector device and a driving circuit for apply the pulses. A nonvolatile memory may include the driving circuit and a plurality of nonvolatile memory elements each including a selector device.

Abstract: A Maclura pubescens extract or fraction or a Prunus cerasoides extract or fraction having neuroglobin (Ngb) activation and neuroprotective effects and, on the basis thereof, a neuroprotective composition containing, as an active ingredient, a Maclura pubescens extract or fraction or a Prunus cerasoides extract or fraction. The neuroprotective composition can be used, through the activation of neuroglobin (Ngb), as a pharmaceutical composition or a food composition for treatment, alleviation and prevention of a stroke, a cerebral infarction, thrombosis, cerebral degenerative disease, vascular dementia, memory loss, short-term memory impairment, a concentration disorder, anxiety, nervousness and the like, and for brain damage protection, brain function improvement and cranial nerve cell protection.

Abstract: A semiconductor device may include active fins spaced apart from each other by a recess therebetween, each of the active fins protruding from an upper surface of a substrate, an isolation structure including a liner on a lower surface and a sidewall of a lower portion of the recess and a blocking pattern on the liner, the blocking pattern filling a remaining portion of the lower portion of the recess and including a nitride, a carbide or polysilicon, a gate electrode structure on the active fins and the isolation structure, and a source/drain layer on a portion of each of the active fins adjacent to the gate electrode structure.

Abstract: A semiconductor device may include active fins spaced apart from each other by a recess therebetween, each of the active fins protruding from an upper surface of a substrate, an isolation structure including a liner on a lower surface and a sidewall of a lower portion of the recess and a blocking pattern on the liner, the blocking pattern filling a remaining portion of the lower portion of the recess and including a nitride, a carbide or polysilicon, a gate electrode structure on the active fins and the isolation structure, and a source/drain layer on a portion of each of the active fins adjacent to the gate electrode structure.

Abstract: Semiconductor devices and methods for fabricating the same are provided. A semiconductor device may include a substrate including first and second regions, a first interface film disposed on the substrate in the first region, a second interface film disposed on the substrate in the second region, a dielectric film disposed on the first and second interface films, a first metal film disposed on the dielectric film in the first region, and a second metal film disposed on the dielectric film in the second region. The first and second interface films may comprise an oxide of the substrate, the first and second metal films may comprise different materials, and the first and second interface films may have different thicknesses. Channels may be provided in the first and second regions, and the channels may be fin-shaped or wire-shaped. The metal films may have different oxygen content.

Abstract: Semiconductor devices may include a substrate including first to third regions, with first to third interfacial layers in the first to third regions, respectively, first to third high-k dielectric films on the first to third interfacial layers, respectively, first to third work function adjustment films on the first to third high-k dielectric films, respectively, and first to third filling films on the first to third work function adjustment films, respectively. Concentrations of a dipole forming element in the first to third high-k dielectric films may be first to third concentrations. The first concentration may be greater than the second concentration, and the second concentration may be greater than the third concentration. Thicknesses of the first to third work function adjustment films may be first to third thicknesses. The first thickness may be less than the second thickness, and the second thickness may be less than the third thickness.

Abstract: Semiconductor devices and methods for fabricating the same are provided. A semiconductor device may include a substrate including first and second regions, a first interface film disposed on the substrate in the first region, a second interface film disposed on the substrate in the second region, a dielectric film disposed on the first and second interface films, a first metal film disposed on the dielectric film in the first region, and a second metal film disposed on the dielectric film in the second region. The first and second interface films may comprise an oxide of the substrate, the first and second metal films may comprise different materials, and the first and second interface films may have different thicknesses. Channels may be provided in the first and second regions, and the channels may be fin-shaped or wire-shaped. The metal films may have different oxygen content.

Abstract: Semiconductor devices may include a substrate including first to third regions, with first to third interfacial layers in the first to third regions, respectively, first to third high-k dielectric films on the first to third interfacial layers, respectively, first to third work function adjustment films on the first to third high-k dielectric films, respectively, and first to third filling films on the first to third work function adjustment films, respectively. Concentrations of a dipole forming element in the first to third high-k dielectric films may be first to third concentrations. The first concentration may be greater than the second concentration, and the second concentration may be greater than the third concentration. Thicknesses of the first to third work function adjustment films may be first to third thicknesses. The first thickness may be less than the second thickness, and the second thickness may be less than the third thickness.

Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.

Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.

Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.

Abstract: In a method of forming a layer, a substrate is loaded into a chamber and placed at a home position that is a first relative angular position. A process cycle is performed a number of times while the substrate is at the home position. The cycle includes directing source gas onto the substrate at a first location adjacent the periphery of the substrate, purging the chamber, directing reaction gas onto the substrate from the first location, and purging the chamber. The cycle is performed another number of times while the substrate is at another relative angular position, i.e., at a position rotated about its general center relative from the home position.

Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.

Abstract: In a method of forming a layer, a substrate is loaded into a chamber and placed at a home position that is a first relative angular position. A process cycle is performed a number of times while the substrate is at the home position. The cycle includes directing source gas onto the substrate at a first location adjacent the periphery of the substrate, purging the chamber, directing reaction gas onto the substrate from the first location, and purging the chamber. The cycle is performed another number of times while the substrate is at another relative angular position, i.e., at a position rotated about its general center relative from the home position.

Abstract: A method for fabricating a semiconductor device comprises forming a gate insulation layer on a substrate including a first region and a second region, forming a first gate conductive layer and a capping layer on the first region and the second region and heat-treating the substrate, removing the capping layer from the first region and the second region, forming a second gate conductive layer on the first region and the second region, nitriding the second gate conductive layer, and forming a third gate conductive layer on the second region.

Abstract: Disclosed herein are novel 1,3-dihydro-5-isobenzofurancarbonitrile derivatives represented by Formula 1, or pharmaceutically acceptable salts thereof. Also disclosed is a pharmaceutical composition for treating or preventing premature ejaculation including the compound. The 1,3-dihydro-5-isobenzofurancarbonitrile derivatives have a short half-life and inhibit the ejaculation process by selectively inhibiting serotonin reuptake via a serotonin reuptake transporter present in a presynaptic neuron. Thus, the compounds are useful in the treatment and prevention of premature ejaculation.

Abstract: Disclosed herein are novel 1,3-dihydro-5-isobenzofurancarbonitrile derivatives represented by Formula 1, or pharmaceutically acceptable salts thereof. Also disclosed is a pharmaceutical composition for treating or preventing premature ejaculation including the compound. The 1,3-dihydro-5-isobenzofurancarbonitrile derivatives have a short half-life and inhibit the ejaculation process by selectively inhibiting serotonin reuptake via a serotonin reuptake transporter present in a presynaptic neuron. Thus, the compounds are useful in the treatment and prevention of premature ejaculation.

Abstract: A MAP provider system for processing SS7 (signalling system No.7) MAP (mobile application part) protocol between MAP user and TCAP (transaction capabilities application part) is provided.

Abstract: A MAP provider system is provided to process SS7 (signalling system No.7) MAP (mobile application part) protocol between MAP user and TCAP (transaction capabilities application part).