Abstract: A semiconductor device, including a plurality of control signal generation units each generating a control signal that is enabled when a column enable signal and a row enable signal are enabled, and a plurality of local sense amplifiers each sensing and amplifying data transmitted via a pair of local input/output (I/O) lines and then outputting the amplified data via a pair of global I/O lines, in response to a read or write signal and a corresponding control signal.

Abstract: A semiconductor device, including a plurality of control signal generation units each generating a control signal that is enabled when a column enable signal and a row enable signal are enabled, and a plurality of local sense amplifiers each sensing and amplifying data transmitted via a pair of local input/output (I/O) lines and then outputting the amplified data via a pair of global I/O lines, in response to a read or write signal and a corresponding control signal.

Abstract: A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh period. The voltage generator generates an output voltage in response to the control signal. The output voltage is boosted from a low voltage to a high voltage during the refresh period. The word line enable circuit generates a word line enable signal in response to the control signal, wherein the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage.

Abstract: Provided are a charge transfer switch circuit for selectively controlling body bias voltage of a charge transfer device, and a boosted voltage generating circuit having the same. The charge transfer switch circuit may include a capacitor whose voltage is boosted based on first and second control signals, a first transistor connected between a supply voltage and the capacitor and having a gate receiving a precharge signal, a second transistor connected between a first node and a second node and having a gate connected to a terminal of the capacitor, a third transistor connected between the first node and a bulk voltage of the second transistor and having a gate receiving the first control signal, and a fourth transistor connected between the bulk voltage of the second transistor and a ground voltage and having a gate receiving the second control signal.

Abstract: A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh period. The voltage generator generates an output voltage in response to the control signal. The output voltage is boosted from a low voltage to a high voltage during the refresh period. The word line enable circuit generates a word line enable signal in response to the control signal, wherein the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage.

Abstract: Provided are a charge transfer switch circuit for selectively controlling body bias voltage of a charge transfer device, and a boosted voltage generating circuit having the same. The charge transfer switch circuit may include a capacitor whose voltage is boosted based on first and second control signals, a first transistor connected between a supply voltage and the capacitor and having a gate receiving a precharge signal, a second transistor connected between a first node and a second node and having a gate connected to a terminal of the capacitor, a third transistor connected between the first node and a bulk voltage of the second transistor and having a gate receiving the first control signal, and a fourth transistor connected between the bulk voltage of the second transistor and a ground voltage and having a gate receiving the second control signal.

Abstract: A row redundancy circuit for use in a semiconductor memory device of the present invention having a fuse box independent of banks so as to improve repair efficiency. The row redundancy circuit includes a fuse box coupled to a row address and a bank address from an address buffer in which a fuse corresponding to an address of a word line to be repaired blows-out, a row fuse decoder for AND-operating two outputs of the fuse box, and a bank row address latch coupled to the output of the row fuse decoder for determining a location of a redundant word line in a block to be repaired.

Abstract: A row redundancy circuit for use in a semiconductor memory device of the present invention having a fuse box independent of banks so as to improve repair efficiency. The row redundancy circuit includes a fuse box coupled to a row address and a bank address from an address buffer in which a fuse corresponding to an address of a word line to be repaired blows-out, a row fuse decoder for AND-operating two outputs of the fuse box, and a bank row address latch coupled to the output of the row fuse decoder for determining a location of a redundant word line in a block to be repaired.