Abstract: Silicon carbide power semiconductor device having uniform channel length and manufacturing method thereof disclosed. The power semiconductor device includes a drift region of a first conductivity type, a plurality of body regions of a second conductivity type, being formed to be spaced apart from each other with a preset WS in a horizontal direction in an upper region of the drift region, a JFET region of the first conductivity type and a low-resistance region of the first conductivity type, being formed in a separation space between adjacent body regions to contact their side surfaces with the adjacent body regions and a source region of the first conductivity type, being formed in a surface region in the body region in contact with the low-resistance region to be spaced apart from the low-resistance region by a preset channel length.

Abstract: A selector according to an embodiment of the present disclosure includes a first electrode; a second electrode disposed opposite to the first electrode; an ion supply layer disposed between the first electrode and the second electrode to be on the side of the first electrode and doped with a metal, wherein the doped metal diffuses toward the second electrode; a switching layer disposed between the first electrode and the second electrode to be on the side of the second electrode, wherein the doped metal diffuses from the ion supply layer into the switching layer so that metal concentration distribution inside the switching layer is changed to generate metal filaments; and a diffusion control layer inserted between the ion supply layer and the switching layer, wherein the diffusion control layer serves to adjust electrical characteristics related to the generated metal filaments as the amount of the diffusing metal is adjusted in proportion to a thickness of the diffusion control layer.

Abstract: A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; and a plurality of pads disposed on the first insulating layer and having top surfaces exposed through the cavity; wherein the cavity of the second insulating layer includes: a bottom surface positioned higher than a top surface of the first insulating layer; and an inner wall extending from the bottom surface, wherein the inner wall is perpendicular to top or bottom surface of the second insulating layer, wherein the bottom surface of the cavity includes: a first bottom surface positioned lower than a top surface of the pad and positioned outside an arrangement region of the plurality of pads; and a second bottom surface positioned lower than the top surface of the pad and positioned inside the arrangement region of the plurality of pads, and wherein a height of the first bottom surface is different from a height of the second bottom surface.

Abstract: Power semiconductor device with dual shield structure in silicon carbide and manufacturing method thereof disclosed.

Abstract: Power semiconductor device with reduced loss and manufacturing method the same disclosed. Power semiconductor device include a first drift region of a first conductivity type, a second drift region of the first conductivity type formed by epitaxially growing on the first drift region and a plurality of buried ion regions of a second conductivity type formed to be buried in the second drift region.

Abstract: Power semiconductor device capable of controlling slope of current and voltage during dynamic switching disclosed. The power semiconductor device may include a semiconductor substrate and a cell array being consisted of a plurality of transistor cells on an active area, wherein each of the plurality of transistor cells may include an emitter region, a body region, a contact region and a gate region, wherein non-uniform threshold voltages may be respectively set in the plurality of transistor cells constituting the cell array, wherein a gate signal may be applied to each of the plurality of transistor cells through an input/output unit, wherein the input/output unit may include a first gate signal path configured for supplying a gate charging current to the gate regions in each of the plurality of transistor cells and a second gate signal path configured for discharging a gate discharging current from the gate region.

Abstract: A method of fabricating a light source includes providing a semiconductor light source emitting light when power is applied thereto, supplying power to the semiconductor light source, receiving light emitted by the semiconductor light source and performing a first measurement of optical properties of the received light, receiving light emitted by the semiconductor light source after a period of time has elapsed from the first measurement and performing a second measurement of optical properties of the received light, determining whether the semiconductor light source is defective or not by comparing the results of the first measurements of optical properties and the second measurements of optical properties, and constructing the light source including the semiconductor light source by providing peripheral parts thereof, wherein the semiconductor light source is determined as being normal as a result of determining whether the semiconductor light source is defective or not.

Abstract: A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.

Abstract: There are provided an apparatus for monitoring bonding surface bouncing, a wire bonding apparatus having the same, and a method for monitoring bonding surface bouncing. According to an aspect of the present invention, the apparatus for monitoring bonding surface bouncing includes a sensor measuring a capillary height in real time during bonding and a bouncing detector extracting a change rate of a capillary height from the capillary height measured in real time during a bonding performing period and detecting of whether bonding surface bouncing is present by comparing the extracted change rate with a set reference change rate.

Abstract: A charge-balance power device and a method of manufacturing the charge-balance power device are provided. The charge-balance power device includes: a charge-balance body region in which one or more first conductive type pillars as a first conductive type impurity region and one or more second conductive type pillars as a second conductive type impurity region are arranged; a first conductive type epitaxial layer that is formed on the charge-balance body region; and a transistor region that is formed in the first conductive type epitaxial layer. With this invention, it is possible to form the same charge-balance body region regardless of the structure of the transistor region formed on the top side of wafer.

Abstract: A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.

Abstract: A MOS-gate power semiconductor device is provided which includes: one or more P-type wells formed under one or more of a gate metal electrode and a gate bus line and electrically connected to an emitter metal electrode; and one or more N-type wells formed in the P-type well and electrically connected to one or more of the gate metal electrode and the gate bus line. According to this configuration, it is possible to suppress deterioration and/or destruction of a device due to an overcurrent.

Abstract: In accordance with the present invention, a transistor includes a semiconductor substrate forming a collector region. A drift region of a first conductivity type extends over the semiconductor substrate. First and second well regions of a second conductivity each extends from an upper surface of the drift region into and terminates within the drift region. The first well region is coupled to an emitter terminal while the second well region floats. The first and second well regions are separated by an impurity region of the first conductivity type such that each of the first and second well regions forms a separate pn junction with the impurity region.

Abstract: A MOS-gated power semiconductor device is described. The MOS-gated power semiconductor device includes a semiconductor substrate that is heavily doped with impurities of a first conductivity type and used as a collector region, a drift region lightly doped with impurities of a second conductivity type on the substrate, a gate insulating layer on the drift region having a center thicker than its edges, a gate electrode on the gate insulating layer, a well region that is lightly doped with impurities of a first conductivity type on the drift region and that has a channel region overlapping a portion of the gate electrode, an emitter region that is heavily doped with impurities of a second conductivity type and that contacts the channel region, an emitter electrode electrically connected to the emitter region and isolated from the gate electrode, and a collector electrode electrically connected to the semiconductor substrate.

Abstract: An insulated gate bipolar transistor having a high breakdown voltage in a reverse blocking mode and a method for fabricating the same are provided. The insulated gate bipolar transistor includes a relatively low-concentration lower buffer layer and a relatively high-concentration upper buffer layer. The low-concentration lower buffer layer contacts a semiconductor substrate having a high concentration of first conductivity type impurities used as a collector region, and the high-concentration upper buffer layer contacts a drift region of a second conductivity type. The conductivity type of the upper buffer layer is second conductivity type impurities, and the conductivity type of the lower buffer layer is substantially intrinsic, or first conductivity type impurities, or second conductivity type impurities. According to the present invention, due to the high-concentration upper buffer layer, the thickness of the drift region can be reduced, and during a forward continuity, a switching speed can be improved.

Abstract: An insulated gate bipolar transistor having a high breakdown voltage in a reverse blocking mode and a method for fabricating the same are provided. The insulated gate bipolar transistor includes a relatively low-concentration lower buffer layer and a relatively high-concentration upper buffer layer. The low-concentration lower buffer layer contacts a semiconductor substrate having a high concentration of first conductivity type impurities used as a collector region, and the high-concentration upper buffer layer contacts a drift region of a second conductivity type. The conductivity type of the upper buffer layer is second conductivity type impurities, and the conductivity type of the lower buffer layer is substantially intrinsic, or first conductivity type impurities, or second conductivity type impurities. According to the present invention, due to the high-concentration upper buffer layer, the thickness of the drift region can be reduced, and during a forward continuity, a switching speed can be improved.

Abstract: A bipolar junction transistor includes a semiconductor substrate having a surface, a base region of first conductivity type in the substrate, and an emitter region of second conductivity type extending from the surface into the base region to form a generally concave semiconductor junction having an apex oriented towards the surface. The emitter region preferably includes a plurality of contiguous emitter subregions extending from the surface into the base region in an arcuate manner and merging to form the generally concave semiconductor junction. The transistor preferably includes an emitter terminal electrically contacting the emitter region at an emitter contact area on the surface, the emitter contact area having a central portion substantially centered with respect to the apex of the semiconductor junction.

Abstract: An insulated gate semiconductor device includes a relatively highly doped epitaxial JFET region. The epitaxial JFET region forms a P-N junction with the base region of the device, but is spaced from the insulated gate electrode by a more lightly doped epitaxial accumulation region. The use of a spaced JFET region provides a number of important performance advantages over prior art power MOSFETs or IGBTs. By spacing the highly doped JFET region from the top face, the devices of the present invention are, among other things, capable of sustaining higher breakdown voltages without a significant increase in forward on-state resistance. For example, by using a more lightly doped accumulation region underneath the gate electrode, in place of a more highly doped JFET region, the punch-through voltage of the device is increased and electric field crowding at the base junction at the top of the face is decreased.

Abstract: A bipolar junction transistor includes a semiconductor substrate having a surface, a base region of first conductivity type in the substrate, and an emitter region of second conductivity type extending from the surface into the base region to form a generally concave semiconductor junction having an apex oriented towards the surface. The emitter region preferably includes a plurality of contiguous emitter subregions extending from the surface into the base region in an arcuate manner and merging to form the generally concave semiconductor junction. The transistor preferably includes an emitter terminal electrically contacting the emitter region at an emitter contact area on the surface, the emitter contact area having a central portion substantially centered with respect to the apex of the semiconductor junction.