Abstract: A touch sensing apparatus that includes a touch panel including first electrodes extending in a first direction and arranged along a second direction, second electrodes extending in the second direction and arranged along the first direction, a signal output unit configured to supply touch driving signals to the first electrodes and configured to receive touch sensing signals generated by the touch driving signals from the first electrodes, and a touch controller configured to calculate a touch position with information from at least one of the first electrodes receiving the touch sensing signals and the first electrodes supplying the touch driving signals corresponding to the touch sensing signals. The second electrodes are connected to corresponding first electrodes and the second electrodes are configured to transfer the touch sensing signals to the corresponding first electrodes.

Abstract: A touch display device according to an exemplary embodiment of the present inventive concept includes: a plurality of pixel circuits; a plurality of first signal lines respectively connected to the plurality of pixel circuits and extending in a first direction; and a plurality of second signal lines respectively connected to the plurality of pixel circuits and extending in a second direction, wherein at least one signal line among the plurality of first signal lines and the plurality of second signal lines function as a first sensing electrode and a second sensing electrode in the touch mode, respectively.

Abstract: An organic light emitting diode display includes a substrate, a transistor on the substrate, a reflecting electrode connected to the transistor, a color filter on the reflecting electrode, a first electrode on the color filter and electrically connected to the reflecting electrode, a pixel definition layer on the color filter and having an opening exposing the first electrode, a white emission layer in the opening and a second electrode on the white emission layer.

Abstract: A display device having an electrostatic discharge protection unit disposed between a display unit and a pad unit. The electrostatic discharge protection unit comprises a first signal line configured to deliver data and a control signal from a pad unit to the display unit, a second signal line, a plurality of first electrostatic discharge protection patterns which are electrically connected to the first signal line; and a plurality of second electrostatic discharge protection patterns which are electrically connected to the second signal line. Respective ones of the first electrostatic discharge protection patterns and the second electrostatic discharge protection patterns together form a plurality of electrostatic discharge protection pattern pairs, and the first and second electrostatic discharge protection patterns in each of the electrostatic discharge protection pattern pairs are separated from each other by differing distances.

Abstract: A display device having a display area including a plurality of pixels and a non-quadrilateral shape, a first gate line in parallel with a first side of a virtual quadrilateral inscribed in the display area, a second gate line in parallel with a second side perpendicular to the first side of the virtual quadrilateral, a first data line in parallel with the first gate line; and a second data line in parallel with the second gate line.

Abstract: A method of driving a display panel includes: generating a data signal having a difference between a number of positive frames and a number of negative frames; and displaying an image according to the data signal.

Abstract: A thin film transistor array panel and a method of manufacturing the same, the thin film transistor array panel including: a polysilicon thin film transistor formed on a substrate, in which a source region and a drain region of a semiconductor layer of the thin film transistor are electrically connected to a power supply line. The power supply line is configured to apply a voltage to remove a floating state of a polysilicon semiconductor layer.

Abstract: Provided is a display panel including: a display area; and a gate driver to receive a first clock signal, a first clock bar signal, a second clock signal and a second clock bar signal, the gate driver comprising a first stage and a second stage to respectively apply a first gate voltage and a second gate voltage to the display area, wherein the first clock signal and the first clock bar signal have opposite phases to each other, the second clock signal and the second clock bar signal have opposite phases to each other, the second clock bar signal has phases later than the first clock bar signal, the first stage discharges the first gate voltage based on the first clock signal and a first transfer signal, and the second stage outputs the first transfer signal based on the second clock bar signal.

Abstract: An organic light emitting display device includes a display panel including data lines, scan lines, initialization lines, and a plurality of pixels, wherein a pixel of the pixels includes: a driving transistor including a gate electrode coupled to a first node, a first electrode coupled to a second node, and a second electrode coupled to a third node, the driving transistor configured to control an amount of a drain-to-source current of the driving transistor according to a voltage applied to the first node; an organic light emitting diode configured to emit light depending on the drain-to-source current of the driving transistor; a first transistor coupled between the second node and a data line of the data lines, the first transistor configured to be turned on by a scan signal applied to a scan line of the scan lines; a second transistor configured to initialize the first node by being turned on; and a first capacitor coupled between the first electrode and the second electrode of the second transistor.

Abstract: A pixel includes a driving transistor, an organic light emitting diode, a first transistor, and the second transistor. The driving transistor includes a gate electrode coupled to a first node, a first electrode coupled to a second node, and a drain electrode coupled to a third node. The driving transistor controls an amount of drain-source current based on a level of a voltage applied to the first node. The first transistor is coupled between the second node and a data line, and turns on by a scan signal of a scan line. The second transistor is coupled between the first node and an initialization voltage line, and turns on by an initialization signal of an initialization line. The first and second transistors are turned on during a first period.

Abstract: A thin film transistor array panel and a method of manufacturing the same, the thin film transistor array panel including: a polysilicon thin film transistor formed on a substrate, in which a source region and a drain region of a semiconductor layer of the thin film transistor are electrically connected to a power supply line. The power supply line is configured to apply a voltage to remove a floating state of a polysilicon semiconductor layer.

Abstract: A display device includes gate lines which transmits a plurality of gate signals, data lines which transmits a plurality of data signals, and pixels connected to the gate lines and the data lines; a signal controller which generates image data, a data control signal and a gate control signal based on an input video signal and an input control signal; a timing setter including connection pads connected to a voltage of a first level or a voltage of a second level; and a gate driver which generates timing information based on tuning signals transmitted from the timing setter through the connection pads and generates gate signals using the gate control signal and the timing information, where the gate control signal includes a scan start reference signal, which instructs a scan start, and a clock control reference signal, which controls each pulse width of the gate signal.

Abstract: Provided is a transmitter for transmitting an orthogonal frequency division multiplexing (OFDM) signal using multiple antennas, including: a subgroup generator to divide data symbols of a frequency domain into a plurality of subgroups; an inverse fast Fourier transform (IFFT) unit to perform an IFFT with respect to each of the subgroups so as to generate partial signals of a time domain corresponding to the plurality of subgroups, respectively; a candidate OFDM signal generator to generate at least two candidate OFDM signals using a combination of the partial signals so that each of the partial signals is transmitted to one of transmit antennas; and a selector to select one of the at least two candidate OFDM signals.

Abstract: A method and apparatus for adaptively transmitting the same data, i.e., multicast/broadcast data, according to channel quality to a receiving group including one or more terminals that request the same service in a wireless network. A base station obtains feedback on channel quality indications (CQIs) from a plurality of terminals, selects a transmission technique that satisfies desired service quality based on the CQIs, and transmits data to the terminals included in a receiving group by using the selected transmission technique. The CQIs to be transmitted from the terminals in the receiving group to the base station are transmitted through a previously allocated common CQI feedback channel. In the present invention, in order to reduce a CQI feedback channel capacity, the base station does not allocate a common CQI feedback channel with respect to each reception terminal and allocates radio resources according to CQI levels.

Abstract: An apparatus for generating a voltage includes a first voltage outputting circuit configured to receive an input voltage and adjust and output a first voltage in accordance with a temperature, a buffer circuit configured to receive the first voltage and output the received first voltage as a second voltage at an output node of the buffer circuit, and a second voltage outputting circuit configured to receive the second voltage at an input terminal and output a third voltage by dividing a driving voltage in accordance with a resistance ratio, wherein the second voltage outputting circuit includes a sub-voltage outputting circuit and a controlling circuit configured to adjust a voltage level of the third voltage through a feedback of the third voltage to the input terminal.

Abstract: A nonvolatile memory device includes an operation voltage generation unit configured to generate a first pass voltage when a verification voltage is higher than a reference voltage and to generate a second pass voltage lower than the first pass voltage when the verification voltage is lower than the reference voltage.

Abstract: Provided is a display panel including: a display area; and a gate driver to receive a first clock signal, a first clock bar signal, a second clock signal and a second clock bar signal, the gate driver comprising a first stage and a second stage to respectively apply a first gate voltage and a second gate voltage to the display area, wherein the first clock signal and the first clock bar signal have opposite phases to each other, the second clock signal and the second clock bar signal have opposite phases to each other, the second clock bar signal has phases later than the first clock bar signal, the first stage discharges the first gate voltage based on the first clock signal and a first transfer signal, and the second stage outputs the first transfer signal based on the second clock bar signal.

Abstract: A method of programming a nonvolatile memory device comprises a bit line voltage set-up step of receiving a program command and data to be programmed and setting up a voltage of a selected bit line according to a state of program data; a program step of supplying a program voltage to a word line selected for a program in response to a control signal for setting up the program voltage, supplying a first pass voltage to unselected word lines, and then performing the program; and a program verification step of, in response to a control signal which is subsequent to the control signal for setting up the program voltage and is used to set a verification voltage, performing a program verification operation by supplying the verification voltage to the selected word line.

Abstract: A nonvolatile memory device includes a high voltage generation unit configured to generate a program voltage and a pass voltage, a block selection unit coupled to the high voltage generation unit through global word lines, a memory cell array coupled to the block selection unit through word lines, a discharge unit coupled to the global word lines and configured to change a level of voltage supplied to the global word lines, and a discharge control unit configured to generate a discharge signal, and transfer the discharge signal to the discharge unit in response to the program voltage.

Abstract: A nonvolatile memory device and a method of operating the same. The nonvolatile memory device includes a memory cell array including memory cells for storing data, a temperature sensor and a controller. The temperature sensor outputs a temperature detection signal according to ambient temperatures while changing one or more pieces of reference voltage information, which are previously stored, when data is programmed into the memory cell array. The controller performs a verify operation of the program using a fast verify method and decides the number of steps which are comprised in step-shaped verify voltage pulse of the fast verify method according to the temperature detection signal.