Abstract: Provided are an SOI substrate, memory devices using the SOI substrate, and a method of manufacturing the same. The SOI substrate includes a thermal oxide layer pattern which minimizes leakage current but allows back biasing and heat dissipation through the substrate. The SOI substrate also includes a metal-gettering site to further minimize leakage current.

Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a metal oxide dielectric layer on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the dielectric layer to form a charge storing region in the dielectric layer with a tunnel dielectric layer under the charge storing region and a capping dielectric layer above the charge storing region. The substrate including the metal oxide dielectric layer is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region. A gate electrode layer is formed on the dielectric layer.

Abstract: An apparatus and method for detecting a surface status. The method includes generating first and second pulse sequences and irradiating the first and second pulse sequences into a given surface. Light from the first and second pulses may be scattered by the given surface and analyzed to determine the status of the given surface. The apparatus includes a device for generating pulses which contact a given surface at different incident angles. The light scattered from the pulses may be analyzed at a determining part to determine a status of the given surface. In another embodiment, the method includes generating first and second pulse sequences and adjusting a path of at least a portion of at least one of the first and second pulse sequences such that the first and second pulse sequences are incident upon a given surface at different incident angles.

Abstract: A susceptor for use in a deposition apparatus includes a recess in which a wafer is received, and a stress-reducing bumper disposed along the side of the recess. The stress-reducing bumper is of material having ductility at a relatively high temperature. Therefore, when the wafer contacts the stress-reducing bumper, such as may occur due to thermal expansion of the wafer during processing, the force of the impact on the wafer is minimized by an elastic deformation of the stress-reducing bumper. As a result, defects, such as slip dislocations at the outer peripheral edge of the wafer, are prevented.