Abstract: A storage device includes a controller configured to receive a pre-processing instruction command from an external device, a non-volatile memory configured to store an original graph data, and a buffer memory connected to the controller and the non-volatile memory, wherein the controller is configured to load the original graph data from the non-volatile memory, generate pre-processing graph data by classifying the original graph data depending on vector similarity in response to the pre-processing instruction command, generate metadata on the basis of the pre-processing graph data, and provide the pre-processing graph data and the metadata to the non-volatile memory, the non-volatile memory is configured to store the pre-processing graph data and the metadata in a data block, and the buffer memory is configured to buffer the original graph data, the pre-processing graph data, and the metadata.

Abstract: A storage device is provided. A storage device includes a non-volatile memory including a plurality of memory segments, and a storage controller connected to the non-volatile memory through a plurality of channels, each of the plurality of channels connected to a respective one of the plurality of memory segments such that each of the plurality of channels has a respective associated memory segment, wherein the storage controller is configured to generate parity according to speed information received from a host with respect to data to be written to the non-volatile memory and store the parity in at least one of the memory segments.

Abstract: A computational storage device includes a control module, and a nonvolatile memory connected to the control module. The nonvolatile memory is configured to store a plurality of graph data elements, which comprises a plurality of nodes and a plurality of edges that connect at least a portion of the plurality of nodes to each other, in a first memory area and a second memory area each having a plurality of blocks and having different read speeds. The control module is configured to store a first graph data element of the plurality of graph data elements having a relatively high degree of association with one node of the plurality of nodes in the first memory area, and store a second graph data element of the plurality of graph data elements having a relatively low degree of association with the one node of the plurality of nodes in the second memory area.

Abstract: Disclosed are a computational storage device, an electronic system and an electronic device. The computational storage device includes a nonvolatile memory, a buffer memory, and a storage controller. The storage controller communicates with the nonvolatile memory and the buffer memory. The storage controller performs computational processing and data format conversion on first data input to the storage controller based on a storage processing table associated with an external electronic device to output second data.

Abstract: A storage device includes a nonvolatile memory device, and a storage controller configured to control the nonvolatile memory device. The storage controller includes: (i) a quality of experience (QoE) manager configured to schedule a request received from an external user equipment, based on storage device information and network information, and (ii) a software-defined networking (SDN) manager configured to set a network transfer path to the external user equipment, which is associated with video data corresponding to the request.

Abstract: A storage device includes a non-volatile memory including a plurality of namespaces including a plurality of logical blocks; and a storage controller configured to, for each of the plurality of namespaces, check a capacity that is a number of allocable logical blocks, among the plurality of logical blocks, and a size that is a sum of a number of currently allocated logical blocks, among the plurality of logical blocks, and the number of allocable logical blocks, detect a first namespace, among the plurality of namespaces, by using the capacity and the size, and provide at least a portion of the allocable logical blocks of a second namespace, among the plurality of namespaces, to the first namespace.

Abstract: A storage device may include a memory, and a storage controller that is configured to generate a hash value, scramble input data with the hash value to generate scrambled data, and store the scrambled data and hash value in association with each other in a memory.

Abstract: The present disclosure provides methods and apparatuses for data loss prevention of a storage device. In some embodiments, the data loss preventing method includes receiving, from a host system, a query plan corresponding to necessary data to be stored in a volatile memory. The data loss preventing method further includes generating, based on the query plan, a data priority list corresponding to the necessary data. The data loss preventing method further includes selecting, based on the data priority list, at least one portion of the volatile memory, when a main power supplied by the host system drops to or below a power level threshold. The data loss preventing method further includes moving the necessary data to the at least one portion of the volatile memory.

Abstract: Disclosed is a storage device including a non-volatile memory that inputs or outputs data at a request of a host system, a volatile memory that temporarily stores data input to or output from the non-volatile memory, an internal spare power source that supplies power to a part of the volatile memory in response to main power supplied from the host system dropping to a first amount or less, and a storage controller that controls the non-volatile memory and the volatile memory. The storage controller is configured to divide the volatile memory into area-received-duplication-power, and at least one area-received-spare-power, in response to the main power dropping to the first amount or less, to redundantly supply spare power to the area-received-duplication-power from an external spare power source and the internal spare power source, and to supply the spare power to the at least one area-received-spare-power from the external spare power source.

Abstract: Disclosed are a storage system and an operation method therefor. The storage system includes: a host system; and a plurality of storage sets configured to interface with the host system. At least one of the plurality of storage sets includes: a first memory region; a second memory region; and a third memory region, and the at least one of the plurality of storage sets is configured to move data stored in the third memory region to a selected memory region among the first memory region and the second memory region based on a data access feature.

Abstract: A method for managing resources by using a processor that includes a first queue and a second queue includes receiving, by the processor, input/output commands from a virtual device, generating, by the processor, interrupts that each includes a process address space identifier (PASID) that corresponds to each of the input/output commands, storing, by the processor, the interrupts in the first queue, storing, by the processor, in a memory device, data that respectively corresponds to each of the interrupts, and storing, by the processor, in the second queue, location information indicating a storage location of the data stored in the memory device and size information indicating a size of the data.

Abstract: The present disclosure provides methods, apparatuses, and servers for cache-coherence. In some embodiments, an apparatus includes a plurality of compute express link (CXL) devices, and a switch. Each CXL device of the plurality of CXL devices includes a memory in which a portion of the memory is allocated as a cache buffer, to which different cache eviction policies are allocated. The different cache eviction policies are modified according to a cache hit ratio of the cache buffer. The switch is configured to connect the plurality of CXL devices to each other.

Abstract: An apparatus including: a plurality of compute express link (CXL) devices each including a memory and a processor for processing works stored in the memory; and a switch configured to connect the CXL devices to each other, wherein a first CXL device among the plurality of CXL devices selects at least one second CXL device from at least some CXL devices of the plurality of CXL devices to distribute works stored in a memory of the first CXL device based on a usable capacity of a memory of the at least some CXL devices.

Abstract: A storage device includes; a memory, a management circuit configured to manage an offloading program table and a count table, and a computing circuit configured to perform a processing operation using the offloading program table, the count table, and the memory. The management circuit is further configured to, in response to a first offloading program and a first offloading request, selectively store the first offloading program in the offloading program table in accordance with a determination of whether an offloading program identical to the first offloading program is stored in the offloading program table, and update the count table storing a first count indicating a remaining number of processing operations using the first offloading program.

Abstract: A storage device is provided. A storage device includes a non-volatile memory including a plurality of memory segments, and a storage controller connected to the non-volatile memory through a plurality of channels, each of the plurality of channels connected to a respective one of the plurality of memory segments such that each of the plurality of channels has a respective associated memory segment, wherein the storage controller is configured to generate parity according to speed information received from a host with respect to data to be written to the non-volatile memory and store the parity in at least one of the memory segments.

Abstract: A storage device includes: a memory device; a memory controller; and a cooling unit configured to guide a flow of a cooling material to the memory controller, wherein the cooling unit includes a housing, a guide member, and a pump, wherein the housing covers the memory controller and includes a first point and a second point, wherein the first point is disposed at a first side of the housing, wherein the second point is disposed at a second side of the housing that is below the first side of the housing, wherein the guide member is attached to the housing and guides the flow of the cooling material from the first point toward the second point, and wherein the pump is configured to adjust an amount of the cooling material flowing from the first point to the second point.

Abstract: A storage device having improved performance and efficiency is provided. A storage device includes a controller configured to receive a pre-processing instruction command from an external device, a non-volatile memory configured to store an original graph data, and a buffer memory connected to the controller and the non-volatile memory, wherein the controller is configured to load the original graph data from the non-volatile memory, generate pre-processing graph data by classifying the original graph data depending on vector similarity in response to the pre-processing instruction command, generate metadata on the basis of the pre-processing graph data, and provide the pre-processing graph data and the metadata to the non-volatile memory, the non-volatile memory is configured to store the pre-processing graph data and the metadata in a data block, and the buffer memory is configured to buffer the original graph data, the pre-processing graph data, and the metadata.

Abstract: A storage device is provided. The storage device includes a controller which receives a command from a host for instructing performance of a first computation, a non-volatile memory which stores a plurality of datasets, a buffer memory to which a first dataset among the plurality of datasets stored in the non-volatile memory is provided in response to the command, and an accelerator which performs the first computation corresponding to the command, using the first dataset provided to the buffer memory. The accelerator includes a memory access module which receives a first input query for instructing the first computation and the first dataset from the buffer memory, and a first computing module which is connected to the memory access module and determines first final candidate data corresponding to the first input query, using the first dataset.

Abstract: An all solid state battery includes: a battery body including an electrode assembly having first and second surfaces in a first direction, third and fourth surfaces in a second direction, and fifth and sixth surfaces in a third direction, and including a solid electrolyte layer and a cathode and an anode; a first connection portion; and a second connection portion disposed on the electrode assembly. The first connection portion includes a first current collecting electrode and a first protection portion, the second connection portion includes a second current collecting electrode and a second protection portion, and the first current collecting electrode is drawn out to one surface of the first connection portion in the third direction and the second current collecting electrode is drawn out to one surface of the second connection portion in the third direction.

Abstract: An electronic component includes: a body having electrical insulating properties; an external electrode disposed on an external surface of the body; and a reinforcing layer disposed on a surface of the body and including a metal oxide layer and a graphene oxide layer.