Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

Abstract: A semiconductor memory device includes first and second memory cell arrays spaced apart from each other in a first direction, a plurality of column selection transistors in a second direction which intersects the first direction, between the first and second memory cell arrays, at least two of the column selection transistors include respective portions of a central gate pattern, which intersects a central line extending in the first direction at a center of the first memory cell array and has a closed loop shape, and first and second local input/output lines configured to provide electric potential through the first memory cell array to a local sense amplifier based on operations of the column selection transistors. The first and second local input/output lines are electrically connected to the central gate pattern, and the center line is spaced apart from and does not intersect the first and second local input/output lines.

Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

Abstract: A semiconductor memory device includes first and second memory cell arrays spaced apart from each other in a first direction, a plurality of column selection transistors in a second direction which intersects the first direction, between the first and second memory cell arrays, at least two of the column selection transistors include respective portions of a central gate pattern, which intersects a central line extending in the first direction at a center of the first memory cell array and has a closed loop shape, and first and second local input/output lines configured to provide electric potential through the first memory cell array to a local sense amplifier based on operations of the column selection transistors. The first and second local input/output lines are electrically connected to the central gate pattern, and the center line is spaced apart from and does not intersect the first and second local input/output lines.

Abstract: A memory circuit and a memory device including the same are provided. The memory circuit may be connected to a bit line and a complementary bit line and configured to perform precharging on the bit line and the complementary bit line. The memory circuit may include: an equalizer configured to equalize voltage levels of the bit line and the complementary bit line by connecting the bit line with the complementary bit line in response to an equalizing signal; and a precharger configured to precharge the bit line and the complementary bit line to a precharge voltage in response to a precharge signal. The equalizing signal and the precharge signal may be received via separate lines.

Abstract: A memory circuit and a memory device including the same are provided. The memory circuit may be connected to a bit line and a complementary bit line and configured to perform precharging on the bit line and the complementary bit line. The memory circuit may include: an equalizer configured to equalize voltage levels of the bit line and the complementary bit line by connecting the bit line with the complementary bit line in response to an equalizing signal; and a precharger configured to precharge the bit line and the complementary bit line to a precharge voltage in response to a precharge signal. The equalizing signal and the precharge signal may be received via separate lines.

Abstract: A circuit for driving a sense amplifier of a semiconductor memory device is provided. The circuit includes a first driving circuit configured to supply a current from a power node to a first driving node of the sense amplifier based on a first driving control signal, a source control circuit configured to generate a control signal based on a second driving control signal and a voltage of the drain node, and a second driving circuit configured to draw current from a second driving node of the sense amplifier to a ground node based on the control signal.

Abstract: A circuit for driving a sense amplifier of a semiconductor memory device is provided. The circuit includes a first driving circuit configured to supply a current from a power node to a first driving node of the sense amplifier based on a first driving control signal, a source control circuit configured to generate a control signal based on a second driving control signal and a voltage of the drain node, and a second driving circuit configured to draw current from a second driving node of the sense amplifier to a ground node based on the control signal.

Abstract: A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.

Abstract: A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.

Abstract: A semiconductor memory device using a full-VDD bit line precharge scheme by using a bit line sense amplifier includes a precharge unit precharging a bit line and a complementary bit line from a power voltage to a voltage that is less than the power voltage by a predetermined voltage, and the bit line sense amplifier including first and second transistors serially connected between the bit line and the complementary bit line to be cross-coupled to each other, wherein a gate of the first transistor is connected to the complementary bit line and a gate of the second transistor is connected to the bit line.

Abstract: A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.

Abstract: A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal.

Abstract: A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.

Abstract: A semiconductor memory device using a full-VDD bit line precharge scheme by using a bit line sense amplifier includes a precharge unit precharging a bit line and a complementary bit line from a power voltage to a voltage that is less than the power voltage by a predetermined voltage, and the bit line sense amplifier including first and second transistors serially connected between the bit line and the complementary bit line to be cross-coupled to each other, wherein a gate of the first transistor is connected to the complementary bit line and a gate of the second transistor is connected to the bit line.

Abstract: Example embodiments may provide a layout structure and layout method for a memory device that may reduce the area of the memory device. Example embodiment layout structures may include a first region and/or a second region. First and second sensing MOS transistors of a sense amplifier that senses data of a bit line and a complementary bit line may be arranged in the first region. First, second and third equalization MOS transistors of an equalizer that equalizes the bit line and the complementary bit line may be arranged In the second region located apart from the first region, Sensing NMOS transistors and equalization NMOS transistors may share an N-type active region in the layout structure of a memory device, and the area of a sense amplifier may be reduced.

Abstract: A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.

Abstract: A bit-line equalizer, a semiconductor memory device including the bit-line equalizer, and a method for manufacturing the bit-line equalizer, in which the bit-line equalizer includes: first and second polysilicon gates formed in a first direction in proximity to each other, the first and second polysilicon gates having a predetermined distance between them; and a plurality of equalizing transistors formed in a second direction along the first and second polysilicon gates, the equalizing transistors equalizing bit-line pairs, with the equalizing transistors being alternately formed in proximity to the first and second polysilicon gates. The bit-line equalizer can vary the widths of the equalizing transistors irrespective of a memory cell pitch in order to improve an equalizing time.

Abstract: A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.

Abstract: Example embodiments may provide a layout structure and layout method for a memory device that may reduce the area of the memory device. Example embodiment layout structures may include a first region and/or a second region. First and second sensing MOS transistors of a sense amplifier that senses data of a bit line and a complementary bit line may be arranged in the first region. First, second and third equalization MOS transistors of an equalizer that equalizes the bit line and the complementary bit line may be arranged In the second region located apart from the first region, Sensing NMOS transistors and equalization NMOS transistors may share an N-type active region in the layout structure of a memory device, and the area of a sense amplifier may be reduced.