Patents by Inventor Soo-Geun Lee
Soo-Geun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11970493Abstract: The present disclosure provides autotaxin (ATX) inhibitor compounds and compositions including said compounds. The present disclosure also provides methods of using said compounds and compositions for inhibiting ATX. Also provided are methods of preparing said compounds and compositions, and synthetic precursors of said compounds.Type: GrantFiled: October 4, 2021Date of Patent: April 30, 2024Assignee: ILDONG PHARMACEUTICAL CO., LTD.Inventors: Sung-Ku Choi, Yoon-Suk Lee, Sung-Wook Kwon, Kyung-Sun Kim, Jeong-Geun Kim, Jeong-Ah Kim, An-Na Moon, Sun-Young Park, Jun-Su Ban, Dong-Keun Song, Kyu-Sic Jang, Ju-Young Jung, Soo-Jin Lee
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Publication number: 20240066110Abstract: The present invention relates to an immunogenic composition including multivalent pneumococcal polysaccharide-protein conjugates. Each conjugate includes capsular polysaccharides of different pneumococcus serotypes conjugated to a carrier protein. More concretely, the present invention is a multivalent immunogenic composition including polysaccharide-protein conjugates. Each of the polysaccharide-protein conjugates includes Streptococcus pneumoniae-derived capsular polysaccharides of different serotypes conjugated to a carrier protein. The capsular polysaccharides include a) capsular polysaccharides of one or more serotypes selected from the group consisting of serotypes 1, 3, 4, 5, 6A, 6B, 7F, 9V, 14, 18C, 19A, 19F, and 23F, and b) capsular polysaccharides of one or more serotypes selected from the group consisting of serotypes 10A, 11A, 12F, 15B, 22F, 23A, and 35B.Type: ApplicationFiled: January 13, 2022Publication date: February 29, 2024Applicant: CELLTRION INC.Inventors: Kyung Min Jo, Pan Kyeom Kim, Wan Geun La, Soo Young Lee, Jun Won Chwa, Ji Hyoun Cha
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Patent number: 7951712Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: GrantFiled: September 9, 2009Date of Patent: May 31, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Publication number: 20100003814Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: ApplicationFiled: September 9, 2009Publication date: January 7, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Patent number: 7605472Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: GrantFiled: February 15, 2007Date of Patent: October 20, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Patent number: 7560332Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.Type: GrantFiled: April 10, 2007Date of Patent: July 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Woo Lee, Wan-Jae Park, Jeong-Hoon Ahn, Kyung-Tae Lee, Mu-Kyeng Jung, Yong-Jun Lee, Il-Goo Kim, Soo-Geun Lee
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Patent number: 7462507Abstract: An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.Type: GrantFiled: October 27, 2004Date of Patent: December 9, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-Geun Lee, Ki-Chul Park, Kyoung-Woo Lee
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Patent number: 7446033Abstract: A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed.Type: GrantFiled: January 23, 2006Date of Patent: November 4, 2008Assignee: Samung Electronics Co., Ltd.Inventors: Sun-jung Lee, Soo-geun Lee, Hong-jae Shin, Andrew-tae Kim, Seung-man Choi, Bong-seok Suh
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Patent number: 7399700Abstract: Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.Type: GrantFiled: August 30, 2007Date of Patent: July 15, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Soo-geun Lee
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Patent number: 7400003Abstract: An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.Type: GrantFiled: November 30, 2004Date of Patent: July 15, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-Geun Lee, Ki-Chul Park, Kyoung-Woo Lee
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Publication number: 20070298580Abstract: Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.Type: ApplicationFiled: August 30, 2007Publication date: December 27, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Soo-geun Lee
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Patent number: 7279733Abstract: Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.Type: GrantFiled: March 12, 2004Date of Patent: October 9, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Soo-geun Lee
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Publication number: 20070184610Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.Type: ApplicationFiled: April 10, 2007Publication date: August 9, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung-woo Lee, Wan-jae Park, Jeong-hoon Ahn, Kyung-tae Lee, Mu-kyeng Jung, Yong-jun Lee, Il-goo Kim, Soo-geun Lee
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Publication number: 20070138642Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: ApplicationFiled: February 15, 2007Publication date: June 21, 2007Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Patent number: 7229875Abstract: Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.Type: GrantFiled: October 16, 2003Date of Patent: June 12, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Wan-jae Park, Jeong-hoon Ahn, Kyung-tae Lee, Mu-kyeng Jung, Yong-jun Lee, Il-goo Kim, Soo-geun Lee
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Patent number: 7205666Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.Type: GrantFiled: March 3, 2006Date of Patent: April 17, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Soo-geun Lee, Ki-chul Park, Won-sang Song
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Publication number: 20070059923Abstract: Methods of fabricating an interconnection line in a semiconductor device and a semiconductor device including such an interconnection line. The method involves forming a lower interconnection line on a semiconductor substrate, forming a mold pattern that defines an opening through which the lower interconnection line is exposed, filling the opening with a conductive material to form a via, removing the mold pattern to make the via remain on the lower interconnection line, forming an interlevel dielectric (ILD) layer that covers the lower interconnection line and the via, patterning the ILD layer, exposing the via, forming a trench that defines a region in which an interconnection line is to be formed, and filling the trench to fabricate a damascene interconnection line connected to the via.Type: ApplicationFiled: June 2, 2006Publication date: March 15, 2007Inventors: Hyo-jong Lee, Ui-hyoung Lee, Hong-jae Shin, Nae-in Lee, Soo-geun Lee
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Patent number: 7183195Abstract: A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.Type: GrantFiled: July 23, 2003Date of Patent: February 27, 2007Assignee: Samsung Electronics, Co., Ltd.Inventors: Kyoung-woo Lee, Soo-geun Lee, Wan-jae Park, Jae-hak Kim, Hong-jae Shin
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Publication number: 20060289999Abstract: A selective copper alloy interconnection in a semiconductor device is provided. The interconnection includes a substrate, a dielectric formed on the substrate, and a first interconnection formed in the dielectric. The first interconnection has a first pure copper pattern. In addition, a second interconnection having a larger width than the first interconnection is formed in the dielectric. The second interconnection has a copper alloy pattern. The copper alloy pattern may be an alloy layer formed of copper (Cu) and an additive material. A method of forming the selective copper alloy pattern is also provided.Type: ApplicationFiled: March 27, 2006Publication date: December 28, 2006Inventors: Hyo-Jong Lee, Sun-Jung Lee, Bong-Seok Suh, Hong-Jae Shin, Nae-In Lee, Kyoung-Woo Lee, Se-Young Jeong, Jeong-Hoon Ahn, Soo-Geun Lee
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Publication number: 20060177630Abstract: A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed.Type: ApplicationFiled: January 23, 2006Publication date: August 10, 2006Inventors: Sun-jung Lee, Soo-geun Lee, Hong-jae Shin, Andrew-tae Kim, Seung-man Choi, Bong-seok Suh